1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Port 4 Control"]
28unsafe impl ::core::marker::Send for super::Port4 {}
29unsafe impl ::core::marker::Sync for super::Port4 {}
30impl super::Port4 {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Port 4 Output Data Register"]
38 #[inline(always)]
39 pub const fn podr4(&self) -> &'static crate::common::Reg<self::Podr4_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Podr4_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "Port 4 Direction Register"]
48 #[inline(always)]
49 pub const fn pdr4(&self) -> &'static crate::common::Reg<self::Pdr4_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Pdr4_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(2usize),
53 )
54 }
55 }
56
57 #[doc = "Port 4 State Register"]
58 #[inline(always)]
59 pub const fn pidr4(&self) -> &'static crate::common::Reg<self::Pidr4_SPEC, crate::common::R> {
60 unsafe {
61 crate::common::Reg::<self::Pidr4_SPEC, crate::common::R>::from_ptr(
62 self._svd2pac_as_ptr().add(6usize),
63 )
64 }
65 }
66
67 #[doc = "Port 4 Output Reset Register"]
68 #[inline(always)]
69 pub const fn porr4(&self) -> &'static crate::common::Reg<self::Porr4_SPEC, crate::common::W> {
70 unsafe {
71 crate::common::Reg::<self::Porr4_SPEC, crate::common::W>::from_ptr(
72 self._svd2pac_as_ptr().add(8usize),
73 )
74 }
75 }
76
77 #[doc = "Port 4 Output Set Register"]
78 #[inline(always)]
79 pub const fn posr4(&self) -> &'static crate::common::Reg<self::Posr4_SPEC, crate::common::W> {
80 unsafe {
81 crate::common::Reg::<self::Posr4_SPEC, crate::common::W>::from_ptr(
82 self._svd2pac_as_ptr().add(10usize),
83 )
84 }
85 }
86}
87#[doc(hidden)]
88#[derive(Copy, Clone, Eq, PartialEq)]
89pub struct Podr4_SPEC;
90impl crate::sealed::RegSpec for Podr4_SPEC {
91 type DataType = u16;
92}
93
94#[doc = "Port 4 Output Data Register"]
95pub type Podr4 = crate::RegValueT<Podr4_SPEC>;
96
97impl Podr4 {
98 #[doc = "P407 Output Data"]
99 #[inline(always)]
100 pub fn podr07(
101 self,
102 ) -> crate::common::RegisterField<
103 7,
104 0x1,
105 1,
106 0,
107 podr4::Podr07,
108 podr4::Podr07,
109 Podr4_SPEC,
110 crate::common::RW,
111 > {
112 crate::common::RegisterField::<
113 7,
114 0x1,
115 1,
116 0,
117 podr4::Podr07,
118 podr4::Podr07,
119 Podr4_SPEC,
120 crate::common::RW,
121 >::from_register(self, 0)
122 }
123}
124impl ::core::default::Default for Podr4 {
125 #[inline(always)]
126 fn default() -> Podr4 {
127 <crate::RegValueT<Podr4_SPEC> as RegisterValue<_>>::new(0)
128 }
129}
130pub mod podr4 {
131
132 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
133 pub struct Podr07_SPEC;
134 pub type Podr07 = crate::EnumBitfieldStruct<u8, Podr07_SPEC>;
135 impl Podr07 {
136 #[doc = "Low output"]
137 pub const _0: Self = Self::new(0);
138
139 #[doc = "High output"]
140 pub const _1: Self = Self::new(1);
141 }
142}
143#[doc(hidden)]
144#[derive(Copy, Clone, Eq, PartialEq)]
145pub struct Pdr4_SPEC;
146impl crate::sealed::RegSpec for Pdr4_SPEC {
147 type DataType = u16;
148}
149
150#[doc = "Port 4 Direction Register"]
151pub type Pdr4 = crate::RegValueT<Pdr4_SPEC>;
152
153impl Pdr4 {
154 #[doc = "P407 Direction"]
155 #[inline(always)]
156 pub fn pdr07(
157 self,
158 ) -> crate::common::RegisterField<
159 7,
160 0x1,
161 1,
162 0,
163 pdr4::Pdr07,
164 pdr4::Pdr07,
165 Pdr4_SPEC,
166 crate::common::RW,
167 > {
168 crate::common::RegisterField::<
169 7,
170 0x1,
171 1,
172 0,
173 pdr4::Pdr07,
174 pdr4::Pdr07,
175 Pdr4_SPEC,
176 crate::common::RW,
177 >::from_register(self, 0)
178 }
179}
180impl ::core::default::Default for Pdr4 {
181 #[inline(always)]
182 fn default() -> Pdr4 {
183 <crate::RegValueT<Pdr4_SPEC> as RegisterValue<_>>::new(0)
184 }
185}
186pub mod pdr4 {
187
188 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
189 pub struct Pdr07_SPEC;
190 pub type Pdr07 = crate::EnumBitfieldStruct<u8, Pdr07_SPEC>;
191 impl Pdr07 {
192 #[doc = "Output 0"]
193 pub const _0: Self = Self::new(0);
194
195 #[doc = "Output 1"]
196 pub const _1: Self = Self::new(1);
197 }
198}
199#[doc(hidden)]
200#[derive(Copy, Clone, Eq, PartialEq)]
201pub struct Pidr4_SPEC;
202impl crate::sealed::RegSpec for Pidr4_SPEC {
203 type DataType = u16;
204}
205
206#[doc = "Port 4 State Register"]
207pub type Pidr4 = crate::RegValueT<Pidr4_SPEC>;
208
209impl Pidr4 {
210 #[doc = "P407 State"]
211 #[inline(always)]
212 pub fn pidr07(
213 self,
214 ) -> crate::common::RegisterField<
215 7,
216 0x1,
217 1,
218 0,
219 pidr4::Pidr07,
220 pidr4::Pidr07,
221 Pidr4_SPEC,
222 crate::common::R,
223 > {
224 crate::common::RegisterField::<
225 7,
226 0x1,
227 1,
228 0,
229 pidr4::Pidr07,
230 pidr4::Pidr07,
231 Pidr4_SPEC,
232 crate::common::R,
233 >::from_register(self, 0)
234 }
235}
236impl ::core::default::Default for Pidr4 {
237 #[inline(always)]
238 fn default() -> Pidr4 {
239 <crate::RegValueT<Pidr4_SPEC> as RegisterValue<_>>::new(0)
240 }
241}
242pub mod pidr4 {
243
244 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
245 pub struct Pidr07_SPEC;
246 pub type Pidr07 = crate::EnumBitfieldStruct<u8, Pidr07_SPEC>;
247 impl Pidr07 {
248 #[doc = "Low level"]
249 pub const _0: Self = Self::new(0);
250
251 #[doc = "High level"]
252 pub const _1: Self = Self::new(1);
253 }
254}
255#[doc(hidden)]
256#[derive(Copy, Clone, Eq, PartialEq)]
257pub struct Porr4_SPEC;
258impl crate::sealed::RegSpec for Porr4_SPEC {
259 type DataType = u16;
260}
261
262#[doc = "Port 4 Output Reset Register"]
263pub type Porr4 = crate::RegValueT<Porr4_SPEC>;
264
265impl Porr4 {
266 #[doc = "P407 Output Reset"]
267 #[inline(always)]
268 pub fn porr07(
269 self,
270 ) -> crate::common::RegisterField<
271 7,
272 0x1,
273 1,
274 0,
275 porr4::Porr07,
276 porr4::Porr07,
277 Porr4_SPEC,
278 crate::common::W,
279 > {
280 crate::common::RegisterField::<
281 7,
282 0x1,
283 1,
284 0,
285 porr4::Porr07,
286 porr4::Porr07,
287 Porr4_SPEC,
288 crate::common::W,
289 >::from_register(self, 0)
290 }
291}
292impl ::core::default::Default for Porr4 {
293 #[inline(always)]
294 fn default() -> Porr4 {
295 <crate::RegValueT<Porr4_SPEC> as RegisterValue<_>>::new(0)
296 }
297}
298pub mod porr4 {
299
300 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
301 pub struct Porr07_SPEC;
302 pub type Porr07 = crate::EnumBitfieldStruct<u8, Porr07_SPEC>;
303 impl Porr07 {
304 #[doc = "No effect on output"]
305 pub const _0: Self = Self::new(0);
306
307 #[doc = "Low output"]
308 pub const _1: Self = Self::new(1);
309 }
310}
311#[doc(hidden)]
312#[derive(Copy, Clone, Eq, PartialEq)]
313pub struct Posr4_SPEC;
314impl crate::sealed::RegSpec for Posr4_SPEC {
315 type DataType = u16;
316}
317
318#[doc = "Port 4 Output Set Register"]
319pub type Posr4 = crate::RegValueT<Posr4_SPEC>;
320
321impl Posr4 {
322 #[doc = "P407 Output Set"]
323 #[inline(always)]
324 pub fn posr07(
325 self,
326 ) -> crate::common::RegisterField<
327 7,
328 0x1,
329 1,
330 0,
331 posr4::Posr07,
332 posr4::Posr07,
333 Posr4_SPEC,
334 crate::common::W,
335 > {
336 crate::common::RegisterField::<
337 7,
338 0x1,
339 1,
340 0,
341 posr4::Posr07,
342 posr4::Posr07,
343 Posr4_SPEC,
344 crate::common::W,
345 >::from_register(self, 0)
346 }
347}
348impl ::core::default::Default for Posr4 {
349 #[inline(always)]
350 fn default() -> Posr4 {
351 <crate::RegValueT<Posr4_SPEC> as RegisterValue<_>>::new(0)
352 }
353}
354pub mod posr4 {
355
356 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
357 pub struct Posr07_SPEC;
358 pub type Posr07 = crate::EnumBitfieldStruct<u8, Posr07_SPEC>;
359 impl Posr07 {
360 #[doc = "No effect on output"]
361 pub const _0: Self = Self::new(0);
362
363 #[doc = "High output"]
364 pub const _1: Self = Self::new(1);
365 }
366}