r528_pac/smhc/
smhc_ntsr.rs

1#[doc = "Register `SMHC_NTSR` reader"]
2pub struct R(crate::R<SMHC_NTSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SMHC_NTSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SMHC_NTSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SMHC_NTSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SMHC_NTSR` writer"]
17pub struct W(crate::W<SMHC_NTSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SMHC_NTSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SMHC_NTSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SMHC_NTSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum MODE_SELECT_A {
40    #[doc = "0: Old mode of Sample/Output Timing"]
41    OLD_MODE = 0,
42    #[doc = "1: New mode of Sample/Output Timing"]
43    NEW_MODE = 1,
44}
45impl From<MODE_SELECT_A> for bool {
46    #[inline(always)]
47    fn from(variant: MODE_SELECT_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `MODE_SELECT` reader - "]
52pub type MODE_SELECT_R = crate::BitReader<MODE_SELECT_A>;
53impl MODE_SELECT_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> MODE_SELECT_A {
57        match self.bits {
58            false => MODE_SELECT_A::OLD_MODE,
59            true => MODE_SELECT_A::NEW_MODE,
60        }
61    }
62    #[doc = "Checks if the value of the field is `OLD_MODE`"]
63    #[inline(always)]
64    pub fn is_old_mode(&self) -> bool {
65        *self == MODE_SELECT_A::OLD_MODE
66    }
67    #[doc = "Checks if the value of the field is `NEW_MODE`"]
68    #[inline(always)]
69    pub fn is_new_mode(&self) -> bool {
70        *self == MODE_SELECT_A::NEW_MODE
71    }
72}
73#[doc = "Field `MODE_SELECT` writer - "]
74pub type MODE_SELECT_W<'a> = crate::BitWriter<'a, u32, SMHC_NTSR_SPEC, MODE_SELECT_A, 31>;
75impl<'a> MODE_SELECT_W<'a> {
76    #[doc = "Old mode of Sample/Output Timing"]
77    #[inline(always)]
78    pub fn old_mode(self) -> &'a mut W {
79        self.variant(MODE_SELECT_A::OLD_MODE)
80    }
81    #[doc = "New mode of Sample/Output Timing"]
82    #[inline(always)]
83    pub fn new_mode(self) -> &'a mut W {
84        self.variant(MODE_SELECT_A::NEW_MODE)
85    }
86}
87#[doc = "Clear the input phase of command lines and data lines during the update clock operation\n\nValue on reset: 0"]
88#[derive(Clone, Copy, Debug, PartialEq)]
89pub enum CMD_DAT_RX_PHASE_CLR_A {
90    #[doc = "0: Disabled"]
91    DISABLED = 0,
92    #[doc = "1: Enabled"]
93    ENABLED = 1,
94}
95impl From<CMD_DAT_RX_PHASE_CLR_A> for bool {
96    #[inline(always)]
97    fn from(variant: CMD_DAT_RX_PHASE_CLR_A) -> Self {
98        variant as u8 != 0
99    }
100}
101#[doc = "Field `CMD_DAT_RX_PHASE_CLR` reader - Clear the input phase of command lines and data lines during the update clock operation"]
102pub type CMD_DAT_RX_PHASE_CLR_R = crate::BitReader<CMD_DAT_RX_PHASE_CLR_A>;
103impl CMD_DAT_RX_PHASE_CLR_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> CMD_DAT_RX_PHASE_CLR_A {
107        match self.bits {
108            false => CMD_DAT_RX_PHASE_CLR_A::DISABLED,
109            true => CMD_DAT_RX_PHASE_CLR_A::ENABLED,
110        }
111    }
112    #[doc = "Checks if the value of the field is `DISABLED`"]
113    #[inline(always)]
114    pub fn is_disabled(&self) -> bool {
115        *self == CMD_DAT_RX_PHASE_CLR_A::DISABLED
116    }
117    #[doc = "Checks if the value of the field is `ENABLED`"]
118    #[inline(always)]
119    pub fn is_enabled(&self) -> bool {
120        *self == CMD_DAT_RX_PHASE_CLR_A::ENABLED
121    }
122}
123#[doc = "Field `CMD_DAT_RX_PHASE_CLR` writer - Clear the input phase of command lines and data lines during the update clock operation"]
124pub type CMD_DAT_RX_PHASE_CLR_W<'a> =
125    crate::BitWriter<'a, u32, SMHC_NTSR_SPEC, CMD_DAT_RX_PHASE_CLR_A, 24>;
126impl<'a> CMD_DAT_RX_PHASE_CLR_W<'a> {
127    #[doc = "Disabled"]
128    #[inline(always)]
129    pub fn disabled(self) -> &'a mut W {
130        self.variant(CMD_DAT_RX_PHASE_CLR_A::DISABLED)
131    }
132    #[doc = "Enabled"]
133    #[inline(always)]
134    pub fn enabled(self) -> &'a mut W {
135        self.variant(CMD_DAT_RX_PHASE_CLR_A::ENABLED)
136    }
137}
138#[doc = "Clear the input phase of data lines before receiving the CRC status\n\nValue on reset: 0"]
139#[derive(Clone, Copy, Debug, PartialEq)]
140pub enum DAT_CRC_STATUS_RX_PHASE_CLR_A {
141    #[doc = "0: Disabled"]
142    DISABLED = 0,
143    #[doc = "1: Enabled"]
144    ENABLED = 1,
145}
146impl From<DAT_CRC_STATUS_RX_PHASE_CLR_A> for bool {
147    #[inline(always)]
148    fn from(variant: DAT_CRC_STATUS_RX_PHASE_CLR_A) -> Self {
149        variant as u8 != 0
150    }
151}
152#[doc = "Field `DAT_CRC_STATUS_RX_PHASE_CLR` reader - Clear the input phase of data lines before receiving the CRC status"]
153pub type DAT_CRC_STATUS_RX_PHASE_CLR_R = crate::BitReader<DAT_CRC_STATUS_RX_PHASE_CLR_A>;
154impl DAT_CRC_STATUS_RX_PHASE_CLR_R {
155    #[doc = "Get enumerated values variant"]
156    #[inline(always)]
157    pub fn variant(&self) -> DAT_CRC_STATUS_RX_PHASE_CLR_A {
158        match self.bits {
159            false => DAT_CRC_STATUS_RX_PHASE_CLR_A::DISABLED,
160            true => DAT_CRC_STATUS_RX_PHASE_CLR_A::ENABLED,
161        }
162    }
163    #[doc = "Checks if the value of the field is `DISABLED`"]
164    #[inline(always)]
165    pub fn is_disabled(&self) -> bool {
166        *self == DAT_CRC_STATUS_RX_PHASE_CLR_A::DISABLED
167    }
168    #[doc = "Checks if the value of the field is `ENABLED`"]
169    #[inline(always)]
170    pub fn is_enabled(&self) -> bool {
171        *self == DAT_CRC_STATUS_RX_PHASE_CLR_A::ENABLED
172    }
173}
174#[doc = "Field `DAT_CRC_STATUS_RX_PHASE_CLR` writer - Clear the input phase of data lines before receiving the CRC status"]
175pub type DAT_CRC_STATUS_RX_PHASE_CLR_W<'a> =
176    crate::BitWriter<'a, u32, SMHC_NTSR_SPEC, DAT_CRC_STATUS_RX_PHASE_CLR_A, 22>;
177impl<'a> DAT_CRC_STATUS_RX_PHASE_CLR_W<'a> {
178    #[doc = "Disabled"]
179    #[inline(always)]
180    pub fn disabled(self) -> &'a mut W {
181        self.variant(DAT_CRC_STATUS_RX_PHASE_CLR_A::DISABLED)
182    }
183    #[doc = "Enabled"]
184    #[inline(always)]
185    pub fn enabled(self) -> &'a mut W {
186        self.variant(DAT_CRC_STATUS_RX_PHASE_CLR_A::ENABLED)
187    }
188}
189#[doc = "Clear the input phase of data lines before transferring the data\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq)]
191pub enum DAT_TRANS_RX_PHASE_CLR_A {
192    #[doc = "0: Disabled"]
193    DISABLED = 0,
194    #[doc = "1: Enabled"]
195    ENABLED = 1,
196}
197impl From<DAT_TRANS_RX_PHASE_CLR_A> for bool {
198    #[inline(always)]
199    fn from(variant: DAT_TRANS_RX_PHASE_CLR_A) -> Self {
200        variant as u8 != 0
201    }
202}
203#[doc = "Field `DAT_TRANS_RX_PHASE_CLR` reader - Clear the input phase of data lines before transferring the data"]
204pub type DAT_TRANS_RX_PHASE_CLR_R = crate::BitReader<DAT_TRANS_RX_PHASE_CLR_A>;
205impl DAT_TRANS_RX_PHASE_CLR_R {
206    #[doc = "Get enumerated values variant"]
207    #[inline(always)]
208    pub fn variant(&self) -> DAT_TRANS_RX_PHASE_CLR_A {
209        match self.bits {
210            false => DAT_TRANS_RX_PHASE_CLR_A::DISABLED,
211            true => DAT_TRANS_RX_PHASE_CLR_A::ENABLED,
212        }
213    }
214    #[doc = "Checks if the value of the field is `DISABLED`"]
215    #[inline(always)]
216    pub fn is_disabled(&self) -> bool {
217        *self == DAT_TRANS_RX_PHASE_CLR_A::DISABLED
218    }
219    #[doc = "Checks if the value of the field is `ENABLED`"]
220    #[inline(always)]
221    pub fn is_enabled(&self) -> bool {
222        *self == DAT_TRANS_RX_PHASE_CLR_A::ENABLED
223    }
224}
225#[doc = "Field `DAT_TRANS_RX_PHASE_CLR` writer - Clear the input phase of data lines before transferring the data"]
226pub type DAT_TRANS_RX_PHASE_CLR_W<'a> =
227    crate::BitWriter<'a, u32, SMHC_NTSR_SPEC, DAT_TRANS_RX_PHASE_CLR_A, 21>;
228impl<'a> DAT_TRANS_RX_PHASE_CLR_W<'a> {
229    #[doc = "Disabled"]
230    #[inline(always)]
231    pub fn disabled(self) -> &'a mut W {
232        self.variant(DAT_TRANS_RX_PHASE_CLR_A::DISABLED)
233    }
234    #[doc = "Enabled"]
235    #[inline(always)]
236    pub fn enabled(self) -> &'a mut W {
237        self.variant(DAT_TRANS_RX_PHASE_CLR_A::ENABLED)
238    }
239}
240#[doc = "Clear the input phase of data lines before receiving the data\n\nValue on reset: 0"]
241#[derive(Clone, Copy, Debug, PartialEq)]
242pub enum DAT_RECV_RX_PHASE_CLR_A {
243    #[doc = "0: Disabled"]
244    DISABLED = 0,
245    #[doc = "1: Enabled"]
246    ENABLED = 1,
247}
248impl From<DAT_RECV_RX_PHASE_CLR_A> for bool {
249    #[inline(always)]
250    fn from(variant: DAT_RECV_RX_PHASE_CLR_A) -> Self {
251        variant as u8 != 0
252    }
253}
254#[doc = "Field `DAT_RECV_RX_PHASE_CLR` reader - Clear the input phase of data lines before receiving the data"]
255pub type DAT_RECV_RX_PHASE_CLR_R = crate::BitReader<DAT_RECV_RX_PHASE_CLR_A>;
256impl DAT_RECV_RX_PHASE_CLR_R {
257    #[doc = "Get enumerated values variant"]
258    #[inline(always)]
259    pub fn variant(&self) -> DAT_RECV_RX_PHASE_CLR_A {
260        match self.bits {
261            false => DAT_RECV_RX_PHASE_CLR_A::DISABLED,
262            true => DAT_RECV_RX_PHASE_CLR_A::ENABLED,
263        }
264    }
265    #[doc = "Checks if the value of the field is `DISABLED`"]
266    #[inline(always)]
267    pub fn is_disabled(&self) -> bool {
268        *self == DAT_RECV_RX_PHASE_CLR_A::DISABLED
269    }
270    #[doc = "Checks if the value of the field is `ENABLED`"]
271    #[inline(always)]
272    pub fn is_enabled(&self) -> bool {
273        *self == DAT_RECV_RX_PHASE_CLR_A::ENABLED
274    }
275}
276#[doc = "Field `DAT_RECV_RX_PHASE_CLR` writer - Clear the input phase of data lines before receiving the data"]
277pub type DAT_RECV_RX_PHASE_CLR_W<'a> =
278    crate::BitWriter<'a, u32, SMHC_NTSR_SPEC, DAT_RECV_RX_PHASE_CLR_A, 20>;
279impl<'a> DAT_RECV_RX_PHASE_CLR_W<'a> {
280    #[doc = "Disabled"]
281    #[inline(always)]
282    pub fn disabled(self) -> &'a mut W {
283        self.variant(DAT_RECV_RX_PHASE_CLR_A::DISABLED)
284    }
285    #[doc = "Enabled"]
286    #[inline(always)]
287    pub fn enabled(self) -> &'a mut W {
288        self.variant(DAT_RECV_RX_PHASE_CLR_A::ENABLED)
289    }
290}
291#[doc = "Clear command rx phase before sending the command\n\nValue on reset: 0"]
292#[derive(Clone, Copy, Debug, PartialEq)]
293pub enum CMD_SEND_RX_PHASE_CLR_A {
294    #[doc = "0: Disabled"]
295    DISABLED = 0,
296    #[doc = "1: Enabled"]
297    ENABLED = 1,
298}
299impl From<CMD_SEND_RX_PHASE_CLR_A> for bool {
300    #[inline(always)]
301    fn from(variant: CMD_SEND_RX_PHASE_CLR_A) -> Self {
302        variant as u8 != 0
303    }
304}
305#[doc = "Field `CMD_SEND_RX_PHASE_CLR` reader - Clear command rx phase before sending the command"]
306pub type CMD_SEND_RX_PHASE_CLR_R = crate::BitReader<CMD_SEND_RX_PHASE_CLR_A>;
307impl CMD_SEND_RX_PHASE_CLR_R {
308    #[doc = "Get enumerated values variant"]
309    #[inline(always)]
310    pub fn variant(&self) -> CMD_SEND_RX_PHASE_CLR_A {
311        match self.bits {
312            false => CMD_SEND_RX_PHASE_CLR_A::DISABLED,
313            true => CMD_SEND_RX_PHASE_CLR_A::ENABLED,
314        }
315    }
316    #[doc = "Checks if the value of the field is `DISABLED`"]
317    #[inline(always)]
318    pub fn is_disabled(&self) -> bool {
319        *self == CMD_SEND_RX_PHASE_CLR_A::DISABLED
320    }
321    #[doc = "Checks if the value of the field is `ENABLED`"]
322    #[inline(always)]
323    pub fn is_enabled(&self) -> bool {
324        *self == CMD_SEND_RX_PHASE_CLR_A::ENABLED
325    }
326}
327#[doc = "Field `CMD_SEND_RX_PHASE_CLR` writer - Clear command rx phase before sending the command"]
328pub type CMD_SEND_RX_PHASE_CLR_W<'a> =
329    crate::BitWriter<'a, u32, SMHC_NTSR_SPEC, CMD_SEND_RX_PHASE_CLR_A, 16>;
330impl<'a> CMD_SEND_RX_PHASE_CLR_W<'a> {
331    #[doc = "Disabled"]
332    #[inline(always)]
333    pub fn disabled(self) -> &'a mut W {
334        self.variant(CMD_SEND_RX_PHASE_CLR_A::DISABLED)
335    }
336    #[doc = "Enabled"]
337    #[inline(always)]
338    pub fn enabled(self) -> &'a mut W {
339        self.variant(CMD_SEND_RX_PHASE_CLR_A::ENABLED)
340    }
341}
342#[doc = "\n\nValue on reset: 0"]
343#[derive(Clone, Copy, Debug, PartialEq)]
344#[repr(u8)]
345pub enum DAT_SAMPLE_TIMING_PHASE_A {
346    #[doc = "0: Sample timing phase offset 90"]
347    O90 = 0,
348    #[doc = "1: Sample timing phase offset 180"]
349    O180 = 1,
350    #[doc = "2: Sample timing phase offset 270"]
351    O270 = 2,
352    #[doc = "3: Sample timing phase offset 0 (only for SD2 hs400 mode)"]
353    O0 = 3,
354}
355impl From<DAT_SAMPLE_TIMING_PHASE_A> for u8 {
356    #[inline(always)]
357    fn from(variant: DAT_SAMPLE_TIMING_PHASE_A) -> Self {
358        variant as _
359    }
360}
361#[doc = "Field `DAT_SAMPLE_TIMING_PHASE` reader - "]
362pub type DAT_SAMPLE_TIMING_PHASE_R = crate::FieldReader<u8, DAT_SAMPLE_TIMING_PHASE_A>;
363impl DAT_SAMPLE_TIMING_PHASE_R {
364    #[doc = "Get enumerated values variant"]
365    #[inline(always)]
366    pub fn variant(&self) -> DAT_SAMPLE_TIMING_PHASE_A {
367        match self.bits {
368            0 => DAT_SAMPLE_TIMING_PHASE_A::O90,
369            1 => DAT_SAMPLE_TIMING_PHASE_A::O180,
370            2 => DAT_SAMPLE_TIMING_PHASE_A::O270,
371            3 => DAT_SAMPLE_TIMING_PHASE_A::O0,
372            _ => unreachable!(),
373        }
374    }
375    #[doc = "Checks if the value of the field is `O90`"]
376    #[inline(always)]
377    pub fn is_o90(&self) -> bool {
378        *self == DAT_SAMPLE_TIMING_PHASE_A::O90
379    }
380    #[doc = "Checks if the value of the field is `O180`"]
381    #[inline(always)]
382    pub fn is_o180(&self) -> bool {
383        *self == DAT_SAMPLE_TIMING_PHASE_A::O180
384    }
385    #[doc = "Checks if the value of the field is `O270`"]
386    #[inline(always)]
387    pub fn is_o270(&self) -> bool {
388        *self == DAT_SAMPLE_TIMING_PHASE_A::O270
389    }
390    #[doc = "Checks if the value of the field is `O0`"]
391    #[inline(always)]
392    pub fn is_o0(&self) -> bool {
393        *self == DAT_SAMPLE_TIMING_PHASE_A::O0
394    }
395}
396#[doc = "Field `DAT_SAMPLE_TIMING_PHASE` writer - "]
397pub type DAT_SAMPLE_TIMING_PHASE_W<'a> =
398    crate::FieldWriterSafe<'a, u32, SMHC_NTSR_SPEC, u8, DAT_SAMPLE_TIMING_PHASE_A, 2, 8>;
399impl<'a> DAT_SAMPLE_TIMING_PHASE_W<'a> {
400    #[doc = "Sample timing phase offset 90"]
401    #[inline(always)]
402    pub fn o90(self) -> &'a mut W {
403        self.variant(DAT_SAMPLE_TIMING_PHASE_A::O90)
404    }
405    #[doc = "Sample timing phase offset 180"]
406    #[inline(always)]
407    pub fn o180(self) -> &'a mut W {
408        self.variant(DAT_SAMPLE_TIMING_PHASE_A::O180)
409    }
410    #[doc = "Sample timing phase offset 270"]
411    #[inline(always)]
412    pub fn o270(self) -> &'a mut W {
413        self.variant(DAT_SAMPLE_TIMING_PHASE_A::O270)
414    }
415    #[doc = "Sample timing phase offset 0 (only for SD2 hs400 mode)"]
416    #[inline(always)]
417    pub fn o0(self) -> &'a mut W {
418        self.variant(DAT_SAMPLE_TIMING_PHASE_A::O0)
419    }
420}
421#[doc = "\n\nValue on reset: 0"]
422#[derive(Clone, Copy, Debug, PartialEq)]
423#[repr(u8)]
424pub enum CMD_SAMPLE_TIMING_PHASE_A {
425    #[doc = "0: Sample timing phase offset 90"]
426    O90 = 0,
427    #[doc = "1: Sample timing phase offset 180"]
428    O180 = 1,
429    #[doc = "2: Sample timing phase offset 270"]
430    O270 = 2,
431    #[doc = "3: Ignore"]
432    O0 = 3,
433}
434impl From<CMD_SAMPLE_TIMING_PHASE_A> for u8 {
435    #[inline(always)]
436    fn from(variant: CMD_SAMPLE_TIMING_PHASE_A) -> Self {
437        variant as _
438    }
439}
440#[doc = "Field `CMD_SAMPLE_TIMING_PHASE` reader - "]
441pub type CMD_SAMPLE_TIMING_PHASE_R = crate::FieldReader<u8, CMD_SAMPLE_TIMING_PHASE_A>;
442impl CMD_SAMPLE_TIMING_PHASE_R {
443    #[doc = "Get enumerated values variant"]
444    #[inline(always)]
445    pub fn variant(&self) -> CMD_SAMPLE_TIMING_PHASE_A {
446        match self.bits {
447            0 => CMD_SAMPLE_TIMING_PHASE_A::O90,
448            1 => CMD_SAMPLE_TIMING_PHASE_A::O180,
449            2 => CMD_SAMPLE_TIMING_PHASE_A::O270,
450            3 => CMD_SAMPLE_TIMING_PHASE_A::O0,
451            _ => unreachable!(),
452        }
453    }
454    #[doc = "Checks if the value of the field is `O90`"]
455    #[inline(always)]
456    pub fn is_o90(&self) -> bool {
457        *self == CMD_SAMPLE_TIMING_PHASE_A::O90
458    }
459    #[doc = "Checks if the value of the field is `O180`"]
460    #[inline(always)]
461    pub fn is_o180(&self) -> bool {
462        *self == CMD_SAMPLE_TIMING_PHASE_A::O180
463    }
464    #[doc = "Checks if the value of the field is `O270`"]
465    #[inline(always)]
466    pub fn is_o270(&self) -> bool {
467        *self == CMD_SAMPLE_TIMING_PHASE_A::O270
468    }
469    #[doc = "Checks if the value of the field is `O0`"]
470    #[inline(always)]
471    pub fn is_o0(&self) -> bool {
472        *self == CMD_SAMPLE_TIMING_PHASE_A::O0
473    }
474}
475#[doc = "Field `CMD_SAMPLE_TIMING_PHASE` writer - "]
476pub type CMD_SAMPLE_TIMING_PHASE_W<'a> =
477    crate::FieldWriterSafe<'a, u32, SMHC_NTSR_SPEC, u8, CMD_SAMPLE_TIMING_PHASE_A, 2, 4>;
478impl<'a> CMD_SAMPLE_TIMING_PHASE_W<'a> {
479    #[doc = "Sample timing phase offset 90"]
480    #[inline(always)]
481    pub fn o90(self) -> &'a mut W {
482        self.variant(CMD_SAMPLE_TIMING_PHASE_A::O90)
483    }
484    #[doc = "Sample timing phase offset 180"]
485    #[inline(always)]
486    pub fn o180(self) -> &'a mut W {
487        self.variant(CMD_SAMPLE_TIMING_PHASE_A::O180)
488    }
489    #[doc = "Sample timing phase offset 270"]
490    #[inline(always)]
491    pub fn o270(self) -> &'a mut W {
492        self.variant(CMD_SAMPLE_TIMING_PHASE_A::O270)
493    }
494    #[doc = "Ignore"]
495    #[inline(always)]
496    pub fn o0(self) -> &'a mut W {
497        self.variant(CMD_SAMPLE_TIMING_PHASE_A::O0)
498    }
499}
500#[doc = "\n\nValue on reset: 0"]
501#[derive(Clone, Copy, Debug, PartialEq)]
502pub enum HS400_NEW_SAMPLE_EN_A {
503    #[doc = "0: Disable hs400 new sample method"]
504    DISABLE = 0,
505    #[doc = "1: Enable hs400 new sample method"]
506    ENABLE = 1,
507}
508impl From<HS400_NEW_SAMPLE_EN_A> for bool {
509    #[inline(always)]
510    fn from(variant: HS400_NEW_SAMPLE_EN_A) -> Self {
511        variant as u8 != 0
512    }
513}
514#[doc = "Field `HS400_NEW_SAMPLE_EN` reader - "]
515pub type HS400_NEW_SAMPLE_EN_R = crate::BitReader<HS400_NEW_SAMPLE_EN_A>;
516impl HS400_NEW_SAMPLE_EN_R {
517    #[doc = "Get enumerated values variant"]
518    #[inline(always)]
519    pub fn variant(&self) -> HS400_NEW_SAMPLE_EN_A {
520        match self.bits {
521            false => HS400_NEW_SAMPLE_EN_A::DISABLE,
522            true => HS400_NEW_SAMPLE_EN_A::ENABLE,
523        }
524    }
525    #[doc = "Checks if the value of the field is `DISABLE`"]
526    #[inline(always)]
527    pub fn is_disable(&self) -> bool {
528        *self == HS400_NEW_SAMPLE_EN_A::DISABLE
529    }
530    #[doc = "Checks if the value of the field is `ENABLE`"]
531    #[inline(always)]
532    pub fn is_enable(&self) -> bool {
533        *self == HS400_NEW_SAMPLE_EN_A::ENABLE
534    }
535}
536#[doc = "Field `HS400_NEW_SAMPLE_EN` writer - "]
537pub type HS400_NEW_SAMPLE_EN_W<'a> =
538    crate::BitWriter<'a, u32, SMHC_NTSR_SPEC, HS400_NEW_SAMPLE_EN_A, 0>;
539impl<'a> HS400_NEW_SAMPLE_EN_W<'a> {
540    #[doc = "Disable hs400 new sample method"]
541    #[inline(always)]
542    pub fn disable(self) -> &'a mut W {
543        self.variant(HS400_NEW_SAMPLE_EN_A::DISABLE)
544    }
545    #[doc = "Enable hs400 new sample method"]
546    #[inline(always)]
547    pub fn enable(self) -> &'a mut W {
548        self.variant(HS400_NEW_SAMPLE_EN_A::ENABLE)
549    }
550}
551impl R {
552    #[doc = "Bit 31"]
553    #[inline(always)]
554    pub fn mode_select(&self) -> MODE_SELECT_R {
555        MODE_SELECT_R::new(((self.bits >> 31) & 1) != 0)
556    }
557    #[doc = "Bit 24 - Clear the input phase of command lines and data lines during the update clock operation"]
558    #[inline(always)]
559    pub fn cmd_dat_rx_phase_clr(&self) -> CMD_DAT_RX_PHASE_CLR_R {
560        CMD_DAT_RX_PHASE_CLR_R::new(((self.bits >> 24) & 1) != 0)
561    }
562    #[doc = "Bit 22 - Clear the input phase of data lines before receiving the CRC status"]
563    #[inline(always)]
564    pub fn dat_crc_status_rx_phase_clr(&self) -> DAT_CRC_STATUS_RX_PHASE_CLR_R {
565        DAT_CRC_STATUS_RX_PHASE_CLR_R::new(((self.bits >> 22) & 1) != 0)
566    }
567    #[doc = "Bit 21 - Clear the input phase of data lines before transferring the data"]
568    #[inline(always)]
569    pub fn dat_trans_rx_phase_clr(&self) -> DAT_TRANS_RX_PHASE_CLR_R {
570        DAT_TRANS_RX_PHASE_CLR_R::new(((self.bits >> 21) & 1) != 0)
571    }
572    #[doc = "Bit 20 - Clear the input phase of data lines before receiving the data"]
573    #[inline(always)]
574    pub fn dat_recv_rx_phase_clr(&self) -> DAT_RECV_RX_PHASE_CLR_R {
575        DAT_RECV_RX_PHASE_CLR_R::new(((self.bits >> 20) & 1) != 0)
576    }
577    #[doc = "Bit 16 - Clear command rx phase before sending the command"]
578    #[inline(always)]
579    pub fn cmd_send_rx_phase_clr(&self) -> CMD_SEND_RX_PHASE_CLR_R {
580        CMD_SEND_RX_PHASE_CLR_R::new(((self.bits >> 16) & 1) != 0)
581    }
582    #[doc = "Bits 8:9"]
583    #[inline(always)]
584    pub fn dat_sample_timing_phase(&self) -> DAT_SAMPLE_TIMING_PHASE_R {
585        DAT_SAMPLE_TIMING_PHASE_R::new(((self.bits >> 8) & 3) as u8)
586    }
587    #[doc = "Bits 4:5"]
588    #[inline(always)]
589    pub fn cmd_sample_timing_phase(&self) -> CMD_SAMPLE_TIMING_PHASE_R {
590        CMD_SAMPLE_TIMING_PHASE_R::new(((self.bits >> 4) & 3) as u8)
591    }
592    #[doc = "Bit 0"]
593    #[inline(always)]
594    pub fn hs400_new_sample_en(&self) -> HS400_NEW_SAMPLE_EN_R {
595        HS400_NEW_SAMPLE_EN_R::new((self.bits & 1) != 0)
596    }
597}
598impl W {
599    #[doc = "Bit 31"]
600    #[inline(always)]
601    pub fn mode_select(&mut self) -> MODE_SELECT_W {
602        MODE_SELECT_W::new(self)
603    }
604    #[doc = "Bit 24 - Clear the input phase of command lines and data lines during the update clock operation"]
605    #[inline(always)]
606    pub fn cmd_dat_rx_phase_clr(&mut self) -> CMD_DAT_RX_PHASE_CLR_W {
607        CMD_DAT_RX_PHASE_CLR_W::new(self)
608    }
609    #[doc = "Bit 22 - Clear the input phase of data lines before receiving the CRC status"]
610    #[inline(always)]
611    pub fn dat_crc_status_rx_phase_clr(&mut self) -> DAT_CRC_STATUS_RX_PHASE_CLR_W {
612        DAT_CRC_STATUS_RX_PHASE_CLR_W::new(self)
613    }
614    #[doc = "Bit 21 - Clear the input phase of data lines before transferring the data"]
615    #[inline(always)]
616    pub fn dat_trans_rx_phase_clr(&mut self) -> DAT_TRANS_RX_PHASE_CLR_W {
617        DAT_TRANS_RX_PHASE_CLR_W::new(self)
618    }
619    #[doc = "Bit 20 - Clear the input phase of data lines before receiving the data"]
620    #[inline(always)]
621    pub fn dat_recv_rx_phase_clr(&mut self) -> DAT_RECV_RX_PHASE_CLR_W {
622        DAT_RECV_RX_PHASE_CLR_W::new(self)
623    }
624    #[doc = "Bit 16 - Clear command rx phase before sending the command"]
625    #[inline(always)]
626    pub fn cmd_send_rx_phase_clr(&mut self) -> CMD_SEND_RX_PHASE_CLR_W {
627        CMD_SEND_RX_PHASE_CLR_W::new(self)
628    }
629    #[doc = "Bits 8:9"]
630    #[inline(always)]
631    pub fn dat_sample_timing_phase(&mut self) -> DAT_SAMPLE_TIMING_PHASE_W {
632        DAT_SAMPLE_TIMING_PHASE_W::new(self)
633    }
634    #[doc = "Bits 4:5"]
635    #[inline(always)]
636    pub fn cmd_sample_timing_phase(&mut self) -> CMD_SAMPLE_TIMING_PHASE_W {
637        CMD_SAMPLE_TIMING_PHASE_W::new(self)
638    }
639    #[doc = "Bit 0"]
640    #[inline(always)]
641    pub fn hs400_new_sample_en(&mut self) -> HS400_NEW_SAMPLE_EN_W {
642        HS400_NEW_SAMPLE_EN_W::new(self)
643    }
644    #[doc = "Writes raw bits to the register."]
645    #[inline(always)]
646    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
647        self.0.bits(bits);
648        self
649    }
650}
651#[doc = "SD New Timing Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smhc_ntsr](index.html) module"]
652pub struct SMHC_NTSR_SPEC;
653impl crate::RegisterSpec for SMHC_NTSR_SPEC {
654    type Ux = u32;
655}
656#[doc = "`read()` method returns [smhc_ntsr::R](R) reader structure"]
657impl crate::Readable for SMHC_NTSR_SPEC {
658    type Reader = R;
659}
660#[doc = "`write(|w| ..)` method takes [smhc_ntsr::W](W) writer structure"]
661impl crate::Writable for SMHC_NTSR_SPEC {
662    type Writer = W;
663}
664#[doc = "`reset()` method sets SMHC_NTSR to value 0"]
665impl crate::Resettable for SMHC_NTSR_SPEC {
666    #[inline(always)]
667    fn reset_value() -> Self::Ux {
668        0
669    }
670}
r528_pac/smhc/smhc_ntsr.rs

r528_pac/smhc/
smhc_ntsr.rs
