r528_pac/dmac/
dmac_irq_en_reg0.rs

1#[doc = "Register `DMAC_IRQ_EN_REG0` reader"]
2pub struct R(crate::R<DMAC_IRQ_EN_REG0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMAC_IRQ_EN_REG0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMAC_IRQ_EN_REG0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMAC_IRQ_EN_REG0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMAC_IRQ_EN_REG0` writer"]
17pub struct W(crate::W<DMAC_IRQ_EN_REG0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMAC_IRQ_EN_REG0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMAC_IRQ_EN_REG0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMAC_IRQ_EN_REG0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Enable the half package interrupt of DMA\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum DMA_HLAF_IRQ_EN_A {
40    #[doc = "0: `0`"]
41    DISABLED = 0,
42    #[doc = "1: `1`"]
43    ENABLED = 1,
44}
45impl From<DMA_HLAF_IRQ_EN_A> for bool {
46    #[inline(always)]
47    fn from(variant: DMA_HLAF_IRQ_EN_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Fields `DMA(0-7)_HLAF_IRQ_EN` reader - Enable the half package interrupt of DMA"]
52pub type DMA_HLAF_IRQ_EN_R = crate::BitReader<DMA_HLAF_IRQ_EN_A>;
53impl DMA_HLAF_IRQ_EN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> DMA_HLAF_IRQ_EN_A {
57        match self.bits {
58            false => DMA_HLAF_IRQ_EN_A::DISABLED,
59            true => DMA_HLAF_IRQ_EN_A::ENABLED,
60        }
61    }
62    #[doc = "Checks if the value of the field is `DISABLED`"]
63    #[inline(always)]
64    pub fn is_disabled(&self) -> bool {
65        *self == DMA_HLAF_IRQ_EN_A::DISABLED
66    }
67    #[doc = "Checks if the value of the field is `ENABLED`"]
68    #[inline(always)]
69    pub fn is_enabled(&self) -> bool {
70        *self == DMA_HLAF_IRQ_EN_A::ENABLED
71    }
72}
73#[doc = "Fields `DMA(0-7)_HLAF_IRQ_EN` writer - Enable the half package interrupt of DMA"]
74pub type DMA_HLAF_IRQ_EN_W<'a, const O: u8> =
75    crate::BitWriter<'a, u32, DMAC_IRQ_EN_REG0_SPEC, DMA_HLAF_IRQ_EN_A, O>;
76impl<'a, const O: u8> DMA_HLAF_IRQ_EN_W<'a, O> {
77    #[doc = "`0`"]
78    #[inline(always)]
79    pub fn disabled(self) -> &'a mut W {
80        self.variant(DMA_HLAF_IRQ_EN_A::DISABLED)
81    }
82    #[doc = "`1`"]
83    #[inline(always)]
84    pub fn enabled(self) -> &'a mut W {
85        self.variant(DMA_HLAF_IRQ_EN_A::ENABLED)
86    }
87}
88#[doc = "Enable the package end interrupt of DMA\n\nValue on reset: 0"]
89#[derive(Clone, Copy, Debug, PartialEq)]
90pub enum DMA_PKG_IRQ_EN_A {
91    #[doc = "0: `0`"]
92    DISABLED = 0,
93    #[doc = "1: `1`"]
94    ENABLED = 1,
95}
96impl From<DMA_PKG_IRQ_EN_A> for bool {
97    #[inline(always)]
98    fn from(variant: DMA_PKG_IRQ_EN_A) -> Self {
99        variant as u8 != 0
100    }
101}
102#[doc = "Fields `DMA(0-7)_PKG_IRQ_EN` reader - Enable the package end interrupt of DMA"]
103pub type DMA_PKG_IRQ_EN_R = crate::BitReader<DMA_PKG_IRQ_EN_A>;
104impl DMA_PKG_IRQ_EN_R {
105    #[doc = "Get enumerated values variant"]
106    #[inline(always)]
107    pub fn variant(&self) -> DMA_PKG_IRQ_EN_A {
108        match self.bits {
109            false => DMA_PKG_IRQ_EN_A::DISABLED,
110            true => DMA_PKG_IRQ_EN_A::ENABLED,
111        }
112    }
113    #[doc = "Checks if the value of the field is `DISABLED`"]
114    #[inline(always)]
115    pub fn is_disabled(&self) -> bool {
116        *self == DMA_PKG_IRQ_EN_A::DISABLED
117    }
118    #[doc = "Checks if the value of the field is `ENABLED`"]
119    #[inline(always)]
120    pub fn is_enabled(&self) -> bool {
121        *self == DMA_PKG_IRQ_EN_A::ENABLED
122    }
123}
124#[doc = "Fields `DMA(0-7)_PKG_IRQ_EN` writer - Enable the package end interrupt of DMA"]
125pub type DMA_PKG_IRQ_EN_W<'a, const O: u8> =
126    crate::BitWriter<'a, u32, DMAC_IRQ_EN_REG0_SPEC, DMA_PKG_IRQ_EN_A, O>;
127impl<'a, const O: u8> DMA_PKG_IRQ_EN_W<'a, O> {
128    #[doc = "`0`"]
129    #[inline(always)]
130    pub fn disabled(self) -> &'a mut W {
131        self.variant(DMA_PKG_IRQ_EN_A::DISABLED)
132    }
133    #[doc = "`1`"]
134    #[inline(always)]
135    pub fn enabled(self) -> &'a mut W {
136        self.variant(DMA_PKG_IRQ_EN_A::ENABLED)
137    }
138}
139#[doc = "Enable the queue end interrupt of DMA\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq)]
141pub enum DMA_QUEUE_IRQ_EN_A {
142    #[doc = "0: `0`"]
143    DISABLED = 0,
144    #[doc = "1: `1`"]
145    ENABLED = 1,
146}
147impl From<DMA_QUEUE_IRQ_EN_A> for bool {
148    #[inline(always)]
149    fn from(variant: DMA_QUEUE_IRQ_EN_A) -> Self {
150        variant as u8 != 0
151    }
152}
153#[doc = "Fields `DMA(0-7)_QUEUE_IRQ_EN` reader - Enable the queue end interrupt of DMA"]
154pub type DMA_QUEUE_IRQ_EN_R = crate::BitReader<DMA_QUEUE_IRQ_EN_A>;
155impl DMA_QUEUE_IRQ_EN_R {
156    #[doc = "Get enumerated values variant"]
157    #[inline(always)]
158    pub fn variant(&self) -> DMA_QUEUE_IRQ_EN_A {
159        match self.bits {
160            false => DMA_QUEUE_IRQ_EN_A::DISABLED,
161            true => DMA_QUEUE_IRQ_EN_A::ENABLED,
162        }
163    }
164    #[doc = "Checks if the value of the field is `DISABLED`"]
165    #[inline(always)]
166    pub fn is_disabled(&self) -> bool {
167        *self == DMA_QUEUE_IRQ_EN_A::DISABLED
168    }
169    #[doc = "Checks if the value of the field is `ENABLED`"]
170    #[inline(always)]
171    pub fn is_enabled(&self) -> bool {
172        *self == DMA_QUEUE_IRQ_EN_A::ENABLED
173    }
174}
175#[doc = "Fields `DMA(0-7)_QUEUE_IRQ_EN` writer - Enable the queue end interrupt of DMA"]
176pub type DMA_QUEUE_IRQ_EN_W<'a, const O: u8> =
177    crate::BitWriter<'a, u32, DMAC_IRQ_EN_REG0_SPEC, DMA_QUEUE_IRQ_EN_A, O>;
178impl<'a, const O: u8> DMA_QUEUE_IRQ_EN_W<'a, O> {
179    #[doc = "`0`"]
180    #[inline(always)]
181    pub fn disabled(self) -> &'a mut W {
182        self.variant(DMA_QUEUE_IRQ_EN_A::DISABLED)
183    }
184    #[doc = "`1`"]
185    #[inline(always)]
186    pub fn enabled(self) -> &'a mut W {
187        self.variant(DMA_QUEUE_IRQ_EN_A::ENABLED)
188    }
189}
190impl R {
191    #[doc = "Enable the half package interrupt of DMA"]
192    #[inline(always)]
193    pub unsafe fn dma_hlaf_irq_en(&self, n: u8) -> DMA_HLAF_IRQ_EN_R {
194        DMA_HLAF_IRQ_EN_R::new(((self.bits >> (n * 4)) & 1) != 0)
195    }
196    #[doc = "Bit 0 - Enable the half package interrupt of DMA"]
197    #[inline(always)]
198    pub fn dma0_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
199        DMA_HLAF_IRQ_EN_R::new((self.bits & 1) != 0)
200    }
201    #[doc = "Bit 4 - Enable the half package interrupt of DMA"]
202    #[inline(always)]
203    pub fn dma1_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
204        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 4) & 1) != 0)
205    }
206    #[doc = "Bit 8 - Enable the half package interrupt of DMA"]
207    #[inline(always)]
208    pub fn dma2_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
209        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 8) & 1) != 0)
210    }
211    #[doc = "Bit 12 - Enable the half package interrupt of DMA"]
212    #[inline(always)]
213    pub fn dma3_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
214        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 12) & 1) != 0)
215    }
216    #[doc = "Bit 16 - Enable the half package interrupt of DMA"]
217    #[inline(always)]
218    pub fn dma4_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
219        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 16) & 1) != 0)
220    }
221    #[doc = "Bit 20 - Enable the half package interrupt of DMA"]
222    #[inline(always)]
223    pub fn dma5_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
224        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 20) & 1) != 0)
225    }
226    #[doc = "Bit 24 - Enable the half package interrupt of DMA"]
227    #[inline(always)]
228    pub fn dma6_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
229        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 24) & 1) != 0)
230    }
231    #[doc = "Bit 28 - Enable the half package interrupt of DMA"]
232    #[inline(always)]
233    pub fn dma7_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
234        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 28) & 1) != 0)
235    }
236    #[doc = "Enable the package end interrupt of DMA"]
237    #[inline(always)]
238    pub unsafe fn dma_pkg_irq_en(&self, n: u8) -> DMA_PKG_IRQ_EN_R {
239        DMA_PKG_IRQ_EN_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
240    }
241    #[doc = "Bit 1 - Enable the package end interrupt of DMA"]
242    #[inline(always)]
243    pub fn dma0_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
244        DMA_PKG_IRQ_EN_R::new(((self.bits >> 1) & 1) != 0)
245    }
246    #[doc = "Bit 5 - Enable the package end interrupt of DMA"]
247    #[inline(always)]
248    pub fn dma1_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
249        DMA_PKG_IRQ_EN_R::new(((self.bits >> 5) & 1) != 0)
250    }
251    #[doc = "Bit 9 - Enable the package end interrupt of DMA"]
252    #[inline(always)]
253    pub fn dma2_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
254        DMA_PKG_IRQ_EN_R::new(((self.bits >> 9) & 1) != 0)
255    }
256    #[doc = "Bit 13 - Enable the package end interrupt of DMA"]
257    #[inline(always)]
258    pub fn dma3_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
259        DMA_PKG_IRQ_EN_R::new(((self.bits >> 13) & 1) != 0)
260    }
261    #[doc = "Bit 17 - Enable the package end interrupt of DMA"]
262    #[inline(always)]
263    pub fn dma4_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
264        DMA_PKG_IRQ_EN_R::new(((self.bits >> 17) & 1) != 0)
265    }
266    #[doc = "Bit 21 - Enable the package end interrupt of DMA"]
267    #[inline(always)]
268    pub fn dma5_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
269        DMA_PKG_IRQ_EN_R::new(((self.bits >> 21) & 1) != 0)
270    }
271    #[doc = "Bit 25 - Enable the package end interrupt of DMA"]
272    #[inline(always)]
273    pub fn dma6_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
274        DMA_PKG_IRQ_EN_R::new(((self.bits >> 25) & 1) != 0)
275    }
276    #[doc = "Bit 29 - Enable the package end interrupt of DMA"]
277    #[inline(always)]
278    pub fn dma7_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
279        DMA_PKG_IRQ_EN_R::new(((self.bits >> 29) & 1) != 0)
280    }
281    #[doc = "Enable the queue end interrupt of DMA"]
282    #[inline(always)]
283    pub unsafe fn dma_queue_irq_en(&self, n: u8) -> DMA_QUEUE_IRQ_EN_R {
284        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0)
285    }
286    #[doc = "Bit 2 - Enable the queue end interrupt of DMA"]
287    #[inline(always)]
288    pub fn dma0_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
289        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 2) & 1) != 0)
290    }
291    #[doc = "Bit 6 - Enable the queue end interrupt of DMA"]
292    #[inline(always)]
293    pub fn dma1_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
294        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 6) & 1) != 0)
295    }
296    #[doc = "Bit 10 - Enable the queue end interrupt of DMA"]
297    #[inline(always)]
298    pub fn dma2_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
299        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 10) & 1) != 0)
300    }
301    #[doc = "Bit 14 - Enable the queue end interrupt of DMA"]
302    #[inline(always)]
303    pub fn dma3_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
304        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 14) & 1) != 0)
305    }
306    #[doc = "Bit 18 - Enable the queue end interrupt of DMA"]
307    #[inline(always)]
308    pub fn dma4_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
309        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 18) & 1) != 0)
310    }
311    #[doc = "Bit 22 - Enable the queue end interrupt of DMA"]
312    #[inline(always)]
313    pub fn dma5_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
314        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 22) & 1) != 0)
315    }
316    #[doc = "Bit 26 - Enable the queue end interrupt of DMA"]
317    #[inline(always)]
318    pub fn dma6_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
319        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 26) & 1) != 0)
320    }
321    #[doc = "Bit 30 - Enable the queue end interrupt of DMA"]
322    #[inline(always)]
323    pub fn dma7_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
324        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 30) & 1) != 0)
325    }
326}
327impl W {
328    #[doc = "Enable the half package interrupt of DMA"]
329    #[inline(always)]
330    pub unsafe fn dma_hlaf_irq_en<const O: u8>(&mut self) -> DMA_HLAF_IRQ_EN_W<O> {
331        DMA_HLAF_IRQ_EN_W::new(self)
332    }
333    #[doc = "Bit 0 - Enable the half package interrupt of DMA"]
334    #[inline(always)]
335    pub fn dma0_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<0> {
336        DMA_HLAF_IRQ_EN_W::new(self)
337    }
338    #[doc = "Bit 4 - Enable the half package interrupt of DMA"]
339    #[inline(always)]
340    pub fn dma1_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<4> {
341        DMA_HLAF_IRQ_EN_W::new(self)
342    }
343    #[doc = "Bit 8 - Enable the half package interrupt of DMA"]
344    #[inline(always)]
345    pub fn dma2_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<8> {
346        DMA_HLAF_IRQ_EN_W::new(self)
347    }
348    #[doc = "Bit 12 - Enable the half package interrupt of DMA"]
349    #[inline(always)]
350    pub fn dma3_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<12> {
351        DMA_HLAF_IRQ_EN_W::new(self)
352    }
353    #[doc = "Bit 16 - Enable the half package interrupt of DMA"]
354    #[inline(always)]
355    pub fn dma4_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<16> {
356        DMA_HLAF_IRQ_EN_W::new(self)
357    }
358    #[doc = "Bit 20 - Enable the half package interrupt of DMA"]
359    #[inline(always)]
360    pub fn dma5_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<20> {
361        DMA_HLAF_IRQ_EN_W::new(self)
362    }
363    #[doc = "Bit 24 - Enable the half package interrupt of DMA"]
364    #[inline(always)]
365    pub fn dma6_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<24> {
366        DMA_HLAF_IRQ_EN_W::new(self)
367    }
368    #[doc = "Bit 28 - Enable the half package interrupt of DMA"]
369    #[inline(always)]
370    pub fn dma7_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<28> {
371        DMA_HLAF_IRQ_EN_W::new(self)
372    }
373    #[doc = "Enable the package end interrupt of DMA"]
374    #[inline(always)]
375    pub unsafe fn dma_pkg_irq_en<const O: u8>(&mut self) -> DMA_PKG_IRQ_EN_W<O> {
376        DMA_PKG_IRQ_EN_W::new(self)
377    }
378    #[doc = "Bit 1 - Enable the package end interrupt of DMA"]
379    #[inline(always)]
380    pub fn dma0_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<1> {
381        DMA_PKG_IRQ_EN_W::new(self)
382    }
383    #[doc = "Bit 5 - Enable the package end interrupt of DMA"]
384    #[inline(always)]
385    pub fn dma1_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<5> {
386        DMA_PKG_IRQ_EN_W::new(self)
387    }
388    #[doc = "Bit 9 - Enable the package end interrupt of DMA"]
389    #[inline(always)]
390    pub fn dma2_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<9> {
391        DMA_PKG_IRQ_EN_W::new(self)
392    }
393    #[doc = "Bit 13 - Enable the package end interrupt of DMA"]
394    #[inline(always)]
395    pub fn dma3_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<13> {
396        DMA_PKG_IRQ_EN_W::new(self)
397    }
398    #[doc = "Bit 17 - Enable the package end interrupt of DMA"]
399    #[inline(always)]
400    pub fn dma4_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<17> {
401        DMA_PKG_IRQ_EN_W::new(self)
402    }
403    #[doc = "Bit 21 - Enable the package end interrupt of DMA"]
404    #[inline(always)]
405    pub fn dma5_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<21> {
406        DMA_PKG_IRQ_EN_W::new(self)
407    }
408    #[doc = "Bit 25 - Enable the package end interrupt of DMA"]
409    #[inline(always)]
410    pub fn dma6_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<25> {
411        DMA_PKG_IRQ_EN_W::new(self)
412    }
413    #[doc = "Bit 29 - Enable the package end interrupt of DMA"]
414    #[inline(always)]
415    pub fn dma7_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<29> {
416        DMA_PKG_IRQ_EN_W::new(self)
417    }
418    #[doc = "Enable the queue end interrupt of DMA"]
419    #[inline(always)]
420    pub unsafe fn dma_queue_irq_en<const O: u8>(&mut self) -> DMA_QUEUE_IRQ_EN_W<O> {
421        DMA_QUEUE_IRQ_EN_W::new(self)
422    }
423    #[doc = "Bit 2 - Enable the queue end interrupt of DMA"]
424    #[inline(always)]
425    pub fn dma0_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<2> {
426        DMA_QUEUE_IRQ_EN_W::new(self)
427    }
428    #[doc = "Bit 6 - Enable the queue end interrupt of DMA"]
429    #[inline(always)]
430    pub fn dma1_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<6> {
431        DMA_QUEUE_IRQ_EN_W::new(self)
432    }
433    #[doc = "Bit 10 - Enable the queue end interrupt of DMA"]
434    #[inline(always)]
435    pub fn dma2_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<10> {
436        DMA_QUEUE_IRQ_EN_W::new(self)
437    }
438    #[doc = "Bit 14 - Enable the queue end interrupt of DMA"]
439    #[inline(always)]
440    pub fn dma3_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<14> {
441        DMA_QUEUE_IRQ_EN_W::new(self)
442    }
443    #[doc = "Bit 18 - Enable the queue end interrupt of DMA"]
444    #[inline(always)]
445    pub fn dma4_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<18> {
446        DMA_QUEUE_IRQ_EN_W::new(self)
447    }
448    #[doc = "Bit 22 - Enable the queue end interrupt of DMA"]
449    #[inline(always)]
450    pub fn dma5_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<22> {
451        DMA_QUEUE_IRQ_EN_W::new(self)
452    }
453    #[doc = "Bit 26 - Enable the queue end interrupt of DMA"]
454    #[inline(always)]
455    pub fn dma6_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<26> {
456        DMA_QUEUE_IRQ_EN_W::new(self)
457    }
458    #[doc = "Bit 30 - Enable the queue end interrupt of DMA"]
459    #[inline(always)]
460    pub fn dma7_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<30> {
461        DMA_QUEUE_IRQ_EN_W::new(self)
462    }
463    #[doc = "Writes raw bits to the register."]
464    #[inline(always)]
465    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
466        self.0.bits(bits);
467        self
468    }
469}
470#[doc = "DMAC IRQ Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac_irq_en_reg0](index.html) module"]
471pub struct DMAC_IRQ_EN_REG0_SPEC;
472impl crate::RegisterSpec for DMAC_IRQ_EN_REG0_SPEC {
473    type Ux = u32;
474}
475#[doc = "`read()` method returns [dmac_irq_en_reg0::R](R) reader structure"]
476impl crate::Readable for DMAC_IRQ_EN_REG0_SPEC {
477    type Reader = R;
478}
479#[doc = "`write(|w| ..)` method takes [dmac_irq_en_reg0::W](W) writer structure"]
480impl crate::Writable for DMAC_IRQ_EN_REG0_SPEC {
481    type Writer = W;
482}
483#[doc = "`reset()` method sets DMAC_IRQ_EN_REG0 to value 0"]
484impl crate::Resettable for DMAC_IRQ_EN_REG0_SPEC {
485    #[inline(always)]
486    fn reset_value() -> Self::Ux {
487        0
488    }
489}
r528_pac/dmac/dmac_irq_en_reg0.rs

r528_pac/dmac/
dmac_irq_en_reg0.rs
