r528_pac/dmac/
dmac_desc_addr_reg.rs

1#[doc = "Register `DMAC_DESC_ADDR_REG%s` reader"]
2pub struct R(crate::R<DMAC_DESC_ADDR_REG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMAC_DESC_ADDR_REG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMAC_DESC_ADDR_REG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMAC_DESC_ADDR_REG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DMAC_DESC_ADDR_REG%s` writer"]
17pub struct W(crate::W<DMAC_DESC_ADDR_REG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DMAC_DESC_ADDR_REG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DMAC_DESC_ADDR_REG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DMAC_DESC_ADDR_REG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DMA_DESC_ADDR` reader - Lower 30 bits of DMA channel descriptor address"]
38pub type DMA_DESC_ADDR_R = crate::FieldReader<u32, u32>;
39#[doc = "Field `DMA_DESC_ADDR` writer - Lower 30 bits of DMA channel descriptor address"]
40pub type DMA_DESC_ADDR_W<'a> =
41    crate::FieldWriter<'a, u32, DMAC_DESC_ADDR_REG_SPEC, u32, u32, 30, 2>;
42#[doc = "Field `DMA_DESC_HIGH_ADDR` reader - Higher 2 bits of DMA channel descriptor high address\n\nDMA Channel Descriptor Address = {bit\\[1:0\\], bit\\[31:2\\], 2'b00}"]
43pub type DMA_DESC_HIGH_ADDR_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `DMA_DESC_HIGH_ADDR` writer - Higher 2 bits of DMA channel descriptor high address\n\nDMA Channel Descriptor Address = {bit\\[1:0\\], bit\\[31:2\\], 2'b00}"]
45pub type DMA_DESC_HIGH_ADDR_W<'a> =
46    crate::FieldWriter<'a, u32, DMAC_DESC_ADDR_REG_SPEC, u8, u8, 2, 0>;
47impl R {
48    #[doc = "Bits 2:31 - Lower 30 bits of DMA channel descriptor address"]
49    #[inline(always)]
50    pub fn dma_desc_addr(&self) -> DMA_DESC_ADDR_R {
51        DMA_DESC_ADDR_R::new(((self.bits >> 2) & 0x3fff_ffff) as u32)
52    }
53    #[doc = "Bits 0:1 - Higher 2 bits of DMA channel descriptor high address\n\nDMA Channel Descriptor Address = {bit\\[1:0\\], bit\\[31:2\\], 2'b00}"]
54    #[inline(always)]
55    pub fn dma_desc_high_addr(&self) -> DMA_DESC_HIGH_ADDR_R {
56        DMA_DESC_HIGH_ADDR_R::new((self.bits & 3) as u8)
57    }
58}
59impl W {
60    #[doc = "Bits 2:31 - Lower 30 bits of DMA channel descriptor address"]
61    #[inline(always)]
62    pub fn dma_desc_addr(&mut self) -> DMA_DESC_ADDR_W {
63        DMA_DESC_ADDR_W::new(self)
64    }
65    #[doc = "Bits 0:1 - Higher 2 bits of DMA channel descriptor high address\n\nDMA Channel Descriptor Address = {bit\\[1:0\\], bit\\[31:2\\], 2'b00}"]
66    #[inline(always)]
67    pub fn dma_desc_high_addr(&mut self) -> DMA_DESC_HIGH_ADDR_W {
68        DMA_DESC_HIGH_ADDR_W::new(self)
69    }
70    #[doc = "Writes raw bits to the register."]
71    #[inline(always)]
72    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
73        self.0.bits(bits);
74        self
75    }
76}
77#[doc = "DMAC Channel Start Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmac_desc_addr_reg](index.html) module"]
78pub struct DMAC_DESC_ADDR_REG_SPEC;
79impl crate::RegisterSpec for DMAC_DESC_ADDR_REG_SPEC {
80    type Ux = u32;
81}
82#[doc = "`read()` method returns [dmac_desc_addr_reg::R](R) reader structure"]
83impl crate::Readable for DMAC_DESC_ADDR_REG_SPEC {
84    type Reader = R;
85}
86#[doc = "`write(|w| ..)` method takes [dmac_desc_addr_reg::W](W) writer structure"]
87impl crate::Writable for DMAC_DESC_ADDR_REG_SPEC {
88    type Writer = W;
89}
90#[doc = "`reset()` method sets DMAC_DESC_ADDR_REG%s to value 0"]
91impl crate::Resettable for DMAC_DESC_ADDR_REG_SPEC {
92    #[inline(always)]
93    fn reset_value() -> Self::Ux {
94        0
95    }
96}
r528_pac/dmac/dmac_desc_addr_reg.rs

r528_pac/dmac/
dmac_desc_addr_reg.rs
