r528_pac/cir_tx/
cir_tglr.rs

1#[doc = "Register `CIR_TGLR` reader"]
2pub struct R(crate::R<CIR_TGLR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CIR_TGLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CIR_TGLR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CIR_TGLR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CIR_TGLR` writer"]
17pub struct W(crate::W<CIR_TGLR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CIR_TGLR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CIR_TGLR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CIR_TGLR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Internal Modulation Select\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum IMS_A {
40    #[doc = "0: The transmitting signal is not modulated"]
41    NOT_MODULATED = 0,
42    #[doc = "1: The transmitting signal is modulated internally"]
43    MODULATED = 1,
44}
45impl From<IMS_A> for bool {
46    #[inline(always)]
47    fn from(variant: IMS_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `IMS` reader - Internal Modulation Select"]
52pub type IMS_R = crate::BitReader<IMS_A>;
53impl IMS_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> IMS_A {
57        match self.bits {
58            false => IMS_A::NOT_MODULATED,
59            true => IMS_A::MODULATED,
60        }
61    }
62    #[doc = "Checks if the value of the field is `NOT_MODULATED`"]
63    #[inline(always)]
64    pub fn is_not_modulated(&self) -> bool {
65        *self == IMS_A::NOT_MODULATED
66    }
67    #[doc = "Checks if the value of the field is `MODULATED`"]
68    #[inline(always)]
69    pub fn is_modulated(&self) -> bool {
70        *self == IMS_A::MODULATED
71    }
72}
73#[doc = "Field `IMS` writer - Internal Modulation Select"]
74pub type IMS_W<'a> = crate::BitWriter<'a, u32, CIR_TGLR_SPEC, IMS_A, 7>;
75impl<'a> IMS_W<'a> {
76    #[doc = "The transmitting signal is not modulated"]
77    #[inline(always)]
78    pub fn not_modulated(self) -> &'a mut W {
79        self.variant(IMS_A::NOT_MODULATED)
80    }
81    #[doc = "The transmitting signal is modulated internally"]
82    #[inline(always)]
83    pub fn modulated(self) -> &'a mut W {
84        self.variant(IMS_A::MODULATED)
85    }
86}
87#[doc = "Duty ratio of modulated carrier is high level/low level.\n\nValue on reset: 0"]
88#[derive(Clone, Copy, Debug, PartialEq)]
89#[repr(u8)]
90pub enum DRMC_A {
91    #[doc = "0: Low level is equal to high level"]
92    EQUAL = 0,
93    #[doc = "1: Low level is the double of high level"]
94    DOUBLE = 1,
95    #[doc = "2: Low level is the triple of high level"]
96    TRIPLE = 2,
97}
98impl From<DRMC_A> for u8 {
99    #[inline(always)]
100    fn from(variant: DRMC_A) -> Self {
101        variant as _
102    }
103}
104#[doc = "Field `DRMC` reader - Duty ratio of modulated carrier is high level/low level."]
105pub type DRMC_R = crate::FieldReader<u8, DRMC_A>;
106impl DRMC_R {
107    #[doc = "Get enumerated values variant"]
108    #[inline(always)]
109    pub fn variant(&self) -> Option<DRMC_A> {
110        match self.bits {
111            0 => Some(DRMC_A::EQUAL),
112            1 => Some(DRMC_A::DOUBLE),
113            2 => Some(DRMC_A::TRIPLE),
114            _ => None,
115        }
116    }
117    #[doc = "Checks if the value of the field is `EQUAL`"]
118    #[inline(always)]
119    pub fn is_equal(&self) -> bool {
120        *self == DRMC_A::EQUAL
121    }
122    #[doc = "Checks if the value of the field is `DOUBLE`"]
123    #[inline(always)]
124    pub fn is_double(&self) -> bool {
125        *self == DRMC_A::DOUBLE
126    }
127    #[doc = "Checks if the value of the field is `TRIPLE`"]
128    #[inline(always)]
129    pub fn is_triple(&self) -> bool {
130        *self == DRMC_A::TRIPLE
131    }
132}
133#[doc = "Field `DRMC` writer - Duty ratio of modulated carrier is high level/low level."]
134pub type DRMC_W<'a> = crate::FieldWriter<'a, u32, CIR_TGLR_SPEC, u8, DRMC_A, 2, 5>;
135impl<'a> DRMC_W<'a> {
136    #[doc = "Low level is equal to high level"]
137    #[inline(always)]
138    pub fn equal(self) -> &'a mut W {
139        self.variant(DRMC_A::EQUAL)
140    }
141    #[doc = "Low level is the double of high level"]
142    #[inline(always)]
143    pub fn double(self) -> &'a mut W {
144        self.variant(DRMC_A::DOUBLE)
145    }
146    #[doc = "Low level is the triple of high level"]
147    #[inline(always)]
148    pub fn triple(self) -> &'a mut W {
149        self.variant(DRMC_A::TRIPLE)
150    }
151}
152#[doc = "Transmit Pulse Polarity Invert\n\nValue on reset: 0"]
153#[derive(Clone, Copy, Debug, PartialEq)]
154pub enum TPPI_A {
155    #[doc = "0: Not invert transmit pulse"]
156    NOT_INVERT = 0,
157    #[doc = "1: Invert transmit pulse"]
158    INVERT = 1,
159}
160impl From<TPPI_A> for bool {
161    #[inline(always)]
162    fn from(variant: TPPI_A) -> Self {
163        variant as u8 != 0
164    }
165}
166#[doc = "Field `TPPI` reader - Transmit Pulse Polarity Invert"]
167pub type TPPI_R = crate::BitReader<TPPI_A>;
168impl TPPI_R {
169    #[doc = "Get enumerated values variant"]
170    #[inline(always)]
171    pub fn variant(&self) -> TPPI_A {
172        match self.bits {
173            false => TPPI_A::NOT_INVERT,
174            true => TPPI_A::INVERT,
175        }
176    }
177    #[doc = "Checks if the value of the field is `NOT_INVERT`"]
178    #[inline(always)]
179    pub fn is_not_invert(&self) -> bool {
180        *self == TPPI_A::NOT_INVERT
181    }
182    #[doc = "Checks if the value of the field is `INVERT`"]
183    #[inline(always)]
184    pub fn is_invert(&self) -> bool {
185        *self == TPPI_A::INVERT
186    }
187}
188#[doc = "Field `TPPI` writer - Transmit Pulse Polarity Invert"]
189pub type TPPI_W<'a> = crate::BitWriter<'a, u32, CIR_TGLR_SPEC, TPPI_A, 2>;
190impl<'a> TPPI_W<'a> {
191    #[doc = "Not invert transmit pulse"]
192    #[inline(always)]
193    pub fn not_invert(self) -> &'a mut W {
194        self.variant(TPPI_A::NOT_INVERT)
195    }
196    #[doc = "Invert transmit pulse"]
197    #[inline(always)]
198    pub fn invert(self) -> &'a mut W {
199        self.variant(TPPI_A::INVERT)
200    }
201}
202#[doc = "Field `TR` reader - Transmit Reset\n\nWhen this bit is set, the transmitting is reset. The FIFO will be flushed, the TIC filed and the CSS field will be cleared during Transmit Reset. This field will automatically be cleared when the Transmit Reset is finished, and the CIR transmitter will state Idle."]
203pub type TR_R = crate::BitReader<bool>;
204#[doc = "Field `TR` writer - Transmit Reset\n\nWhen this bit is set, the transmitting is reset. The FIFO will be flushed, the TIC filed and the CSS field will be cleared during Transmit Reset. This field will automatically be cleared when the Transmit Reset is finished, and the CIR transmitter will state Idle."]
205pub type TR_W<'a> = crate::BitWriter<'a, u32, CIR_TGLR_SPEC, bool, 1>;
206#[doc = "Transmit Block Enable\n\nValue on reset: 0"]
207#[derive(Clone, Copy, Debug, PartialEq)]
208pub enum TXEN_A {
209    #[doc = "0: Disable the CIR Transmitter"]
210    DISABLE = 0,
211    #[doc = "1: Enable the CIR Transmitter"]
212    ENABLE = 1,
213}
214impl From<TXEN_A> for bool {
215    #[inline(always)]
216    fn from(variant: TXEN_A) -> Self {
217        variant as u8 != 0
218    }
219}
220#[doc = "Field `TXEN` reader - Transmit Block Enable"]
221pub type TXEN_R = crate::BitReader<TXEN_A>;
222impl TXEN_R {
223    #[doc = "Get enumerated values variant"]
224    #[inline(always)]
225    pub fn variant(&self) -> TXEN_A {
226        match self.bits {
227            false => TXEN_A::DISABLE,
228            true => TXEN_A::ENABLE,
229        }
230    }
231    #[doc = "Checks if the value of the field is `DISABLE`"]
232    #[inline(always)]
233    pub fn is_disable(&self) -> bool {
234        *self == TXEN_A::DISABLE
235    }
236    #[doc = "Checks if the value of the field is `ENABLE`"]
237    #[inline(always)]
238    pub fn is_enable(&self) -> bool {
239        *self == TXEN_A::ENABLE
240    }
241}
242#[doc = "Field `TXEN` writer - Transmit Block Enable"]
243pub type TXEN_W<'a> = crate::BitWriter<'a, u32, CIR_TGLR_SPEC, TXEN_A, 0>;
244impl<'a> TXEN_W<'a> {
245    #[doc = "Disable the CIR Transmitter"]
246    #[inline(always)]
247    pub fn disable(self) -> &'a mut W {
248        self.variant(TXEN_A::DISABLE)
249    }
250    #[doc = "Enable the CIR Transmitter"]
251    #[inline(always)]
252    pub fn enable(self) -> &'a mut W {
253        self.variant(TXEN_A::ENABLE)
254    }
255}
256impl R {
257    #[doc = "Bit 7 - Internal Modulation Select"]
258    #[inline(always)]
259    pub fn ims(&self) -> IMS_R {
260        IMS_R::new(((self.bits >> 7) & 1) != 0)
261    }
262    #[doc = "Bits 5:6 - Duty ratio of modulated carrier is high level/low level."]
263    #[inline(always)]
264    pub fn drmc(&self) -> DRMC_R {
265        DRMC_R::new(((self.bits >> 5) & 3) as u8)
266    }
267    #[doc = "Bit 2 - Transmit Pulse Polarity Invert"]
268    #[inline(always)]
269    pub fn tppi(&self) -> TPPI_R {
270        TPPI_R::new(((self.bits >> 2) & 1) != 0)
271    }
272    #[doc = "Bit 1 - Transmit Reset\n\nWhen this bit is set, the transmitting is reset. The FIFO will be flushed, the TIC filed and the CSS field will be cleared during Transmit Reset. This field will automatically be cleared when the Transmit Reset is finished, and the CIR transmitter will state Idle."]
273    #[inline(always)]
274    pub fn tr(&self) -> TR_R {
275        TR_R::new(((self.bits >> 1) & 1) != 0)
276    }
277    #[doc = "Bit 0 - Transmit Block Enable"]
278    #[inline(always)]
279    pub fn txen(&self) -> TXEN_R {
280        TXEN_R::new((self.bits & 1) != 0)
281    }
282}
283impl W {
284    #[doc = "Bit 7 - Internal Modulation Select"]
285    #[inline(always)]
286    pub fn ims(&mut self) -> IMS_W {
287        IMS_W::new(self)
288    }
289    #[doc = "Bits 5:6 - Duty ratio of modulated carrier is high level/low level."]
290    #[inline(always)]
291    pub fn drmc(&mut self) -> DRMC_W {
292        DRMC_W::new(self)
293    }
294    #[doc = "Bit 2 - Transmit Pulse Polarity Invert"]
295    #[inline(always)]
296    pub fn tppi(&mut self) -> TPPI_W {
297        TPPI_W::new(self)
298    }
299    #[doc = "Bit 1 - Transmit Reset\n\nWhen this bit is set, the transmitting is reset. The FIFO will be flushed, the TIC filed and the CSS field will be cleared during Transmit Reset. This field will automatically be cleared when the Transmit Reset is finished, and the CIR transmitter will state Idle."]
300    #[inline(always)]
301    pub fn tr(&mut self) -> TR_W {
302        TR_W::new(self)
303    }
304    #[doc = "Bit 0 - Transmit Block Enable"]
305    #[inline(always)]
306    pub fn txen(&mut self) -> TXEN_W {
307        TXEN_W::new(self)
308    }
309    #[doc = "Writes raw bits to the register."]
310    #[inline(always)]
311    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
312        self.0.bits(bits);
313        self
314    }
315}
316#[doc = "CIR Transmit Global Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cir_tglr](index.html) module"]
317pub struct CIR_TGLR_SPEC;
318impl crate::RegisterSpec for CIR_TGLR_SPEC {
319    type Ux = u32;
320}
321#[doc = "`read()` method returns [cir_tglr::R](R) reader structure"]
322impl crate::Readable for CIR_TGLR_SPEC {
323    type Reader = R;
324}
325#[doc = "`write(|w| ..)` method takes [cir_tglr::W](W) writer structure"]
326impl crate::Writable for CIR_TGLR_SPEC {
327    type Writer = W;
328}
329#[doc = "`reset()` method sets CIR_TGLR to value 0"]
330impl crate::Resettable for CIR_TGLR_SPEC {
331    #[inline(always)]
332    fn reset_value() -> Self::Ux {
333        0
334    }
335}
r528_pac/cir_tx/cir_tglr.rs

r528_pac/cir_tx/
cir_tglr.rs
