1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - PLL_CPU Control Register"]
5 pub pll_cpu_ctrl: crate::Reg<pll_cpu_ctrl::PLL_CPU_CTRL_SPEC>,
6 _reserved1: [u8; 0x0c],
7 #[doc = "0x10 - PLL_DDR Control Register"]
8 pub pll_ddr_ctrl: crate::Reg<pll_ddr_ctrl::PLL_DDR_CTRL_SPEC>,
9 _reserved2: [u8; 0x0c],
10 #[doc = "0x20 - PLL_PERI Control Register"]
11 pub pll_peri_ctrl: crate::Reg<pll_peri_ctrl::PLL_PERI_CTRL_SPEC>,
12 _reserved3: [u8; 0x1c],
13 #[doc = "0x40 - PLL_VIDEO0 Control Register"]
14 pub pll_video0_ctrl: crate::Reg<pll_video0_ctrl::PLL_VIDEO0_CTRL_SPEC>,
15 _reserved4: [u8; 0x04],
16 #[doc = "0x48 - PLL_VIDEO1 Control Register"]
17 pub pll_video1_ctrl: crate::Reg<pll_video1_ctrl::PLL_VIDEO1_CTRL_SPEC>,
18 _reserved5: [u8; 0x0c],
19 #[doc = "0x58 - PLL_VE Control Register"]
20 pub pll_ve_ctrl: crate::Reg<pll_ve_ctrl::PLL_VE_CTRL_SPEC>,
21 _reserved6: [u8; 0x1c],
22 #[doc = "0x78 - PLL_AUDIO0 Control Register"]
23 pub pll_audio0_ctrl: crate::Reg<pll_audio0_ctrl::PLL_AUDIO0_CTRL_SPEC>,
24 _reserved7: [u8; 0x04],
25 #[doc = "0x80 - PLL_AUDIO1 Control Register"]
26 pub pll_audio1_ctrl: crate::Reg<pll_audio1_ctrl::PLL_AUDIO1_CTRL_SPEC>,
27 _reserved8: [u8; 0x8c],
28 #[doc = "0x110 - PLL_DDR Pattern0 Control Register"]
29 pub pll_ddr_pat0_ctrl: crate::Reg<pll_ddr_pat0_ctrl::PLL_DDR_PAT0_CTRL_SPEC>,
30 #[doc = "0x114 - PLL_DDR Pattern1 Control Register"]
31 pub pll_ddr_pat1_ctrl: crate::Reg<pll_ddr_pat1_ctrl::PLL_DDR_PAT1_CTRL_SPEC>,
32 _reserved10: [u8; 0x08],
33 #[doc = "0x120 - PLL_PERI Pattern0 Control Register"]
34 pub pll_peri_pat0_ctrl: crate::Reg<pll_peri_pat0_ctrl::PLL_PERI_PAT0_CTRL_SPEC>,
35 #[doc = "0x124 - PLL_PERI Pattern1 Control Register"]
36 pub pll_peri_pat1_ctrl: crate::Reg<pll_peri_pat1_ctrl::PLL_PERI_PAT1_CTRL_SPEC>,
37 _reserved12: [u8; 0x18],
38 #[doc = "0x140 - PLL_VIDEO0 Pattern0 Control Register"]
39 pub pll_video0_pat0_ctrl: crate::Reg<pll_video0_pat0_ctrl::PLL_VIDEO0_PAT0_CTRL_SPEC>,
40 #[doc = "0x144 - PLL_VIDEO0 Pattern1 Control Register"]
41 pub pll_video0_pat1_ctrl: crate::Reg<pll_video0_pat1_ctrl::PLL_VIDEO0_PAT1_CTRL_SPEC>,
42 #[doc = "0x148 - PLL_VIDEO1 Pattern0 Control Register"]
43 pub pll_video1_pat0_ctrl: crate::Reg<pll_video1_pat0_ctrl::PLL_VIDEO1_PAT0_CTRL_SPEC>,
44 #[doc = "0x14c - PLL_VIDEO1 Pattern1 Control Register"]
45 pub pll_video1_pat1_ctrl: crate::Reg<pll_video1_pat1_ctrl::PLL_VIDEO1_PAT1_CTRL_SPEC>,
46 _reserved16: [u8; 0x08],
47 #[doc = "0x158 - PLL_VE Pattern0 Control Register"]
48 pub pll_ve_pat0_ctrl: crate::Reg<pll_ve_pat0_ctrl::PLL_VE_PAT0_CTRL_SPEC>,
49 #[doc = "0x15c - PLL_VE Pattern1 Control Register"]
50 pub pll_ve_pat1_ctrl: crate::Reg<pll_ve_pat1_ctrl::PLL_VE_PAT1_CTRL_SPEC>,
51 _reserved18: [u8; 0x18],
52 #[doc = "0x178 - PLL_AUDIO0 Pattern0 Control Register"]
53 pub pll_audio0_pat0_ctrl: crate::Reg<pll_audio0_pat0_ctrl::PLL_AUDIO0_PAT0_CTRL_SPEC>,
54 #[doc = "0x17c - PLL_AUDIO0 Pattern1 Control Register"]
55 pub pll_audio0_pat1_ctrl: crate::Reg<pll_audio0_pat1_ctrl::PLL_AUDIO0_PAT1_CTRL_SPEC>,
56 #[doc = "0x180 - PLL_AUDIO1 Pattern0 Control Register"]
57 pub pll_audio1_pat0_ctrl: crate::Reg<pll_audio1_pat0_ctrl::PLL_AUDIO1_PAT0_CTRL_SPEC>,
58 #[doc = "0x184 - PLL_AUDIO1 Pattern1 Control Register"]
59 pub pll_audio1_pat1_ctrl: crate::Reg<pll_audio1_pat1_ctrl::PLL_AUDIO1_PAT1_CTRL_SPEC>,
60 _reserved22: [u8; 0x0178],
61 #[doc = "0x300 - PLL_CPU Bias Register"]
62 pub pll_cpu_bias: crate::Reg<pll_cpu_bias::PLL_CPU_BIAS_SPEC>,
63 _reserved23: [u8; 0x0c],
64 #[doc = "0x310 - PLL_DDR Bias Register"]
65 pub pll_ddr_bias: crate::Reg<pll_ddr_bias::PLL_DDR_BIAS_SPEC>,
66 _reserved24: [u8; 0x0c],
67 #[doc = "0x320 - PLL_PERI Bias Register"]
68 pub pll_peri_bias: crate::Reg<pll_peri_bias::PLL_PERI_BIAS_SPEC>,
69 _reserved25: [u8; 0x1c],
70 #[doc = "0x340 - PLL_VIDEO0 Bias Register"]
71 pub pll_video0_bias: crate::Reg<pll_video0_bias::PLL_VIDEO0_BIAS_SPEC>,
72 _reserved26: [u8; 0x04],
73 #[doc = "0x348 - PLL_VIDEO1 Bias Register"]
74 pub pll_video1_bias: crate::Reg<pll_video1_bias::PLL_VIDEO1_BIAS_SPEC>,
75 _reserved27: [u8; 0x0c],
76 #[doc = "0x358 - PLL_VE Bias Register"]
77 pub pll_ve_bias: crate::Reg<pll_ve_bias::PLL_VE_BIAS_SPEC>,
78 _reserved28: [u8; 0x1c],
79 #[doc = "0x378 - PLL_AUDIO0 Bias Register"]
80 pub pll_audio0_bias: crate::Reg<pll_audio0_bias::PLL_AUDIO0_BIAS_SPEC>,
81 _reserved29: [u8; 0x04],
82 #[doc = "0x380 - PLL_AUDIO1 Bias Register"]
83 pub pll_audio1_bias: crate::Reg<pll_audio1_bias::PLL_AUDIO1_BIAS_SPEC>,
84 _reserved30: [u8; 0x7c],
85 #[doc = "0x400 - PLL_CPU Tuning Register"]
86 pub pll_cpu_tun: crate::Reg<pll_cpu_tun::PLL_CPU_TUN_SPEC>,
87 _reserved31: [u8; 0xfc],
88 #[doc = "0x500 - CPU_AXI Configuration Register"]
89 pub cpu_axi_cfg: crate::Reg<cpu_axi_cfg::CPU_AXI_CFG_SPEC>,
90 #[doc = "0x504 - CPU_GATING Configuration Register"]
91 pub cpu_gating: crate::Reg<cpu_gating::CPU_GATING_SPEC>,
92 _reserved33: [u8; 0x08],
93 #[doc = "0x510 - PSI Clock Register"]
94 pub psi_clk: crate::Reg<psi_clk::PSI_CLK_SPEC>,
95 _reserved34: [u8; 0x0c],
96 #[doc = "0x520..0x528 - APB Clock Register"]
97 pub apb_clk: [crate::Reg<apb_clk::APB_CLK_SPEC>; 2],
98 _reserved35: [u8; 0x18],
99 #[doc = "0x540 - MBUS Clock Register"]
100 pub mbus_clk: crate::Reg<mbus_clk::MBUS_CLK_SPEC>,
101 _reserved36: [u8; 0xbc],
102 #[doc = "0x600 - DE Clock Register"]
103 pub de_clk: crate::Reg<de_clk::DE_CLK_SPEC>,
104 _reserved37: [u8; 0x08],
105 #[doc = "0x60c - DE Bus Gating Reset Register"]
106 pub de_bgr: crate::Reg<de_bgr::DE_BGR_SPEC>,
107 _reserved38: [u8; 0x10],
108 #[doc = "0x620 - DI Clock Register"]
109 pub di_clk: crate::Reg<di_clk::DI_CLK_SPEC>,
110 _reserved39: [u8; 0x08],
111 #[doc = "0x62c - DI Bus Gating Reset Register"]
112 pub di_bgr: crate::Reg<di_bgr::DI_BGR_SPEC>,
113 #[doc = "0x630 - G2D Clock Register"]
114 pub g2d_clk: crate::Reg<g2d_clk::G2D_CLK_SPEC>,
115 _reserved41: [u8; 0x08],
116 #[doc = "0x63c - G2D Bus Gating Reset Register"]
117 pub g2d_bgr: crate::Reg<g2d_bgr::G2D_BGR_SPEC>,
118 _reserved42: [u8; 0x40],
119 #[doc = "0x680 - CE Clock Register"]
120 pub ce_clk: crate::Reg<ce_clk::CE_CLK_SPEC>,
121 _reserved43: [u8; 0x08],
122 #[doc = "0x68c - CE Bus Gating Reset Register"]
123 pub ce_bgr: crate::Reg<ce_bgr::CE_BGR_SPEC>,
124 #[doc = "0x690 - VE Clock Register"]
125 pub ve_clk: crate::Reg<ve_clk::VE_CLK_SPEC>,
126 _reserved45: [u8; 0x08],
127 #[doc = "0x69c - VE Bus Gating Reset Register"]
128 pub ve_bgr: crate::Reg<ve_bgr::VE_BGR_SPEC>,
129 _reserved46: [u8; 0x6c],
130 #[doc = "0x70c - DMA Bus Gating Reset Register"]
131 pub dma_bgr: crate::Reg<dma_bgr::DMA_BGR_SPEC>,
132 _reserved47: [u8; 0x0c],
133 #[doc = "0x71c - MSGBOX Bus Gating Reset Register"]
134 pub msgbox_bgr: crate::Reg<msgbox_bgr::MSGBOX_BGR_SPEC>,
135 _reserved48: [u8; 0x0c],
136 #[doc = "0x72c - SPINLOCK Bus Gating Reset Register"]
137 pub spinlock_bgr: crate::Reg<spinlock_bgr::SPINLOCK_BGR_SPEC>,
138 _reserved49: [u8; 0x0c],
139 #[doc = "0x73c - HSTIMER Bus Gating Reset Register"]
140 pub hstimer_bgr: crate::Reg<hstimer_bgr::HSTIMER_BGR_SPEC>,
141 #[doc = "0x740 - AVS Clock Register"]
142 pub avs_clk: crate::Reg<avs_clk::AVS_CLK_SPEC>,
143 _reserved51: [u8; 0x48],
144 #[doc = "0x78c - DBGSYS Bus Gating Reset Register"]
145 pub dbgsys_bgr: crate::Reg<dbgsys_bgr::DBGSYS_BGR_SPEC>,
146 _reserved52: [u8; 0x1c],
147 #[doc = "0x7ac - PWM Bus Gating Reset Register"]
148 pub pwm_bgr: crate::Reg<pwm_bgr::PWM_BGR_SPEC>,
149 _reserved53: [u8; 0x0c],
150 #[doc = "0x7bc - IOMMU Bus Gating Reset Register"]
151 pub iommu_bgr: crate::Reg<iommu_bgr::IOMMU_BGR_SPEC>,
152 _reserved54: [u8; 0x40],
153 #[doc = "0x800 - DRAM Clock Register"]
154 pub dram_clk: crate::Reg<dram_clk::DRAM_CLK_SPEC>,
155 #[doc = "0x804 - MBUS Master Clock Gating Register"]
156 pub mbus_mat_clk_gating: crate::Reg<mbus_mat_clk_gating::MBUS_MAT_CLK_GATING_SPEC>,
157 _reserved56: [u8; 0x04],
158 #[doc = "0x80c - DRAM Bus Gating Reset Register"]
159 pub dram_bgr: crate::Reg<dram_bgr::DRAM_BGR_SPEC>,
160 _reserved57: [u8; 0x20],
161 #[doc = "0x830 - SMHC0 Clock Register"]
162 pub smhc0_clk: crate::Reg<smhc0_clk::SMHC0_CLK_SPEC>,
163 #[doc = "0x834 - SMHC1 Clock Register"]
164 pub smhc1_clk: crate::Reg<smhc1_clk::SMHC1_CLK_SPEC>,
165 #[doc = "0x838 - SMHC2 Clock Register"]
166 pub smhc2_clk: crate::Reg<smhc2_clk::SMHC2_CLK_SPEC>,
167 _reserved60: [u8; 0x10],
168 #[doc = "0x84c - SMHC Bus Gating Reset Register"]
169 pub smhc_bgr: crate::Reg<smhc_bgr::SMHC_BGR_SPEC>,
170 _reserved61: [u8; 0xbc],
171 #[doc = "0x90c - UART Bus Gating Reset Register"]
172 pub uart_bgr: crate::Reg<uart_bgr::UART_BGR_SPEC>,
173 _reserved62: [u8; 0x0c],
174 #[doc = "0x91c - TWI Bus Gating Reset Register"]
175 pub twi_bgr: crate::Reg<twi_bgr::TWI_BGR_SPEC>,
176 _reserved63: [u8; 0x20],
177 #[doc = "0x940 - SPI0 Clock Register"]
178 pub spi0_clk: crate::Reg<spi0_clk::SPI0_CLK_SPEC>,
179 #[doc = "0x944 - SPI1 Clock Register"]
180 pub spi1_clk: crate::Reg<spi1_clk::SPI1_CLK_SPEC>,
181 _reserved65: [u8; 0x24],
182 #[doc = "0x96c - SPI Bus Gating Reset Register"]
183 pub spi_bgr: crate::Reg<spi_bgr::SPI_BGR_SPEC>,
184 #[doc = "0x970 - EMAC_25M Clock Register"]
185 pub emac_25m_clk: crate::Reg<emac_25m_clk::EMAC_25M_CLK_SPEC>,
186 _reserved67: [u8; 0x08],
187 #[doc = "0x97c - EMAC Bus Gating Reset Register"]
188 pub emac_bgr: crate::Reg<emac_bgr::EMAC_BGR_SPEC>,
189 _reserved68: [u8; 0x40],
190 #[doc = "0x9c0 - IRTX Clock Register"]
191 pub irtx_clk: crate::Reg<irtx_clk::IRTX_CLK_SPEC>,
192 _reserved69: [u8; 0x08],
193 #[doc = "0x9cc - IRTX Bus Gating Reset Register"]
194 pub irtx_bgr: crate::Reg<irtx_bgr::IRTX_BGR_SPEC>,
195 _reserved70: [u8; 0x1c],
196 #[doc = "0x9ec - GPADC Bus Gating Reset Register"]
197 pub gpadc_bgr: crate::Reg<gpadc_bgr::GPADC_BGR_SPEC>,
198 _reserved71: [u8; 0x0c],
199 #[doc = "0x9fc - THS Bus Gating Reset Register"]
200 pub ths_bgr: crate::Reg<ths_bgr::THS_BGR_SPEC>,
201 _reserved72: [u8; 0x10],
202 #[doc = "0xa10..0xa1c - I2S Clock Register"]
203 pub i2s_clk: [crate::Reg<i2s_clk::I2S_CLK_SPEC>; 3],
204 #[doc = "0xa1c - I2S2_ASRC Clock Register"]
205 pub i2s2_asrc_clk: crate::Reg<i2s2_asrc_clk::I2S2_ASRC_CLK_SPEC>,
206 #[doc = "0xa20 - I2S Bus Gating Reset Register"]
207 pub i2s_bgr: crate::Reg<i2s_bgr::I2S_BGR_SPEC>,
208 #[doc = "0xa24 - OWA_TX Clock Register"]
209 pub owa_tx_clk: crate::Reg<owa_tx_clk::OWA_TX_CLK_SPEC>,
210 #[doc = "0xa28 - OWA_RX Clock Register"]
211 pub owa_rx_clk: crate::Reg<owa_rx_clk::OWA_RX_CLK_SPEC>,
212 #[doc = "0xa2c - OWA Bus Gating Reset Register"]
213 pub owa_bgr: crate::Reg<owa_bgr::OWA_BGR_SPEC>,
214 _reserved78: [u8; 0x10],
215 #[doc = "0xa40 - DMIC Clock Register"]
216 pub dmic_clk: crate::Reg<dmic_clk::DMIC_CLK_SPEC>,
217 _reserved79: [u8; 0x08],
218 #[doc = "0xa4c - DMIC Bus Gating Reset Register"]
219 pub dmic_bgr: crate::Reg<dmic_bgr::DMIC_BGR_SPEC>,
220 #[doc = "0xa50 - AUDIO_CODEC_DAC Clock Register"]
221 pub audio_codec_dac_clk: crate::Reg<audio_codec_dac_clk::AUDIO_CODEC_DAC_CLK_SPEC>,
222 #[doc = "0xa54 - AUDIO_CODEC_ADC Clock Register"]
223 pub audio_codec_adc_clk: crate::Reg<audio_codec_adc_clk::AUDIO_CODEC_ADC_CLK_SPEC>,
224 _reserved82: [u8; 0x04],
225 #[doc = "0xa5c - AUDIO_CODEC Bus Gating Reset Register"]
226 pub audio_codec_bgr: crate::Reg<audio_codec_bgr::AUDIO_CODEC_BGR_SPEC>,
227 _reserved83: [u8; 0x10],
228 #[doc = "0xa70 - USB0 Clock Register"]
229 pub usb0_clk: crate::Reg<usb0_clk::USB0_CLK_SPEC>,
230 #[doc = "0xa74 - USB1 Clock Register"]
231 pub usb1_clk: crate::Reg<usb1_clk::USB1_CLK_SPEC>,
232 _reserved85: [u8; 0x14],
233 #[doc = "0xa8c - USB Bus Gating Reset Register"]
234 pub usb_bgr: crate::Reg<usb_bgr::USB_BGR_SPEC>,
235 _reserved86: [u8; 0x0c],
236 #[doc = "0xa9c - LRADC Bus Gating Reset Register"]
237 pub lradc_bgr: crate::Reg<lradc_bgr::LRADC_BGR_SPEC>,
238 _reserved87: [u8; 0x1c],
239 #[doc = "0xabc - DPSS_TOP Bus Gating Reset Register"]
240 pub dpss_top_bgr: crate::Reg<dpss_top_bgr::DPSS_TOP_BGR_SPEC>,
241 _reserved88: [u8; 0x64],
242 #[doc = "0xb24 - DSI Clock Register"]
243 pub dsi_clk: crate::Reg<dsi_clk::DSI_CLK_SPEC>,
244 _reserved89: [u8; 0x24],
245 #[doc = "0xb4c - DSI Bus Gating Reset Register"]
246 pub dsi_bgr: crate::Reg<dsi_bgr::DSI_BGR_SPEC>,
247 _reserved90: [u8; 0x10],
248 #[doc = "0xb60 - TCONLCD Clock Register"]
249 pub tconlcd_clk: crate::Reg<tconlcd_clk::TCONLCD_CLK_SPEC>,
250 _reserved91: [u8; 0x18],
251 #[doc = "0xb7c - TCONLCD Bus Gating Reset Register"]
252 pub tconlcd_bgr: crate::Reg<tconlcd_bgr::TCONLCD_BGR_SPEC>,
253 #[doc = "0xb80 - TCONTV Clock Register"]
254 pub tcontv_clk: crate::Reg<tcontv_clk::TCONTV_CLK_SPEC>,
255 _reserved93: [u8; 0x18],
256 #[doc = "0xb9c - TCONTV Bus Gating Reset Register"]
257 pub tcontv_bgr: crate::Reg<tcontv_bgr::TCONTV_BGR_SPEC>,
258 _reserved94: [u8; 0x0c],
259 #[doc = "0xbac - LVDS Bus Gating Reset Register"]
260 pub lvds_bgr: crate::Reg<lvds_bgr::LVDS_BGR_SPEC>,
261 #[doc = "0xbb0 - TVE Clock Register"]
262 pub tve_clk: crate::Reg<tve_clk::TVE_CLK_SPEC>,
263 _reserved96: [u8; 0x08],
264 #[doc = "0xbbc - TVE Bus Gating Reset Register"]
265 pub tve_bgr: crate::Reg<tve_bgr::TVE_BGR_SPEC>,
266 #[doc = "0xbc0 - TVD Clock Register"]
267 pub tvd_clk: crate::Reg<tvd_clk::TVD_CLK_SPEC>,
268 _reserved98: [u8; 0x18],
269 #[doc = "0xbdc - TVD Bus Gating Reset Register"]
270 pub tvd_bgr: crate::Reg<tvd_bgr::TVD_BGR_SPEC>,
271 _reserved99: [u8; 0x10],
272 #[doc = "0xbf0 - LEDC Clock Register"]
273 pub ledc_clk: crate::Reg<ledc_clk::LEDC_CLK_SPEC>,
274 _reserved100: [u8; 0x08],
275 #[doc = "0xbfc - LEDC Bus Gating Reset Register"]
276 pub ledc_bgr: crate::Reg<ledc_bgr::LEDC_BGR_SPEC>,
277 _reserved101: [u8; 0x04],
278 #[doc = "0xc04 - CSI Clock Register"]
279 pub csi_clk: crate::Reg<csi_clk::CSI_CLK_SPEC>,
280 #[doc = "0xc08 - CSI Master Clock Register"]
281 pub csi_master_clk: crate::Reg<csi_master_clk::CSI_MASTER_CLK_SPEC>,
282 _reserved103: [u8; 0x10],
283 #[doc = "0xc1c - CSI Bus Gating Reset Register"]
284 pub csi_bgr: crate::Reg<csi_bgr::CSI_BGR_SPEC>,
285 _reserved104: [u8; 0x30],
286 #[doc = "0xc50 - TPADC Clock Register"]
287 pub tpadc_clk: crate::Reg<tpadc_clk::TPADC_CLK_SPEC>,
288 _reserved105: [u8; 0x08],
289 #[doc = "0xc5c - TPADC Bus Gating Reset Register"]
290 pub tpadc_bgr: crate::Reg<tpadc_bgr::TPADC_BGR_SPEC>,
291 _reserved106: [u8; 0x10],
292 #[doc = "0xc70 - DSP Clock Register"]
293 pub dsp_clk: crate::Reg<dsp_clk::DSP_CLK_SPEC>,
294 _reserved107: [u8; 0x08],
295 #[doc = "0xc7c - DSP Bus Gating Reset Register"]
296 pub dsp_bgr: crate::Reg<dsp_bgr::DSP_BGR_SPEC>,
297 _reserved108: [u8; 0x80],
298 #[doc = "0xd00 - RISC-V Clock Register"]
299 pub riscv_clk: crate::Reg<riscv_clk::RISCV_CLK_SPEC>,
300 #[doc = "0xd04 - RISC-V GATING Configuration Register"]
301 pub riscv_gating: crate::Reg<riscv_gating::RISCV_GATING_SPEC>,
302 _reserved110: [u8; 0x04],
303 #[doc = "0xd0c - RISC-V_CFG Bus Gating Reset Register"]
304 pub riscv_cfg_bgr: crate::Reg<riscv_cfg_bgr::RISCV_CFG_BGR_SPEC>,
305 _reserved111: [u8; 0x01f4],
306 #[doc = "0xf04 - PLL Lock Debug Control Register"]
307 pub pll_lock_dbg_ctrl: crate::Reg<pll_lock_dbg_ctrl::PLL_LOCK_DBG_CTRL_SPEC>,
308 #[doc = "0xf08 - Frequency Detect Control Register"]
309 pub fre_det_ctrl: crate::Reg<fre_det_ctrl::FRE_DET_CTRL_SPEC>,
310 #[doc = "0xf0c - Frequency Up Limit Register"]
311 pub fre_up_lim: crate::Reg<fre_up_lim::FRE_UP_LIM_SPEC>,
312 #[doc = "0xf10 - Frequency Down Limit Register"]
313 pub fre_down_lim: crate::Reg<fre_down_lim::FRE_DOWN_LIM_SPEC>,
314 _reserved115: [u8; 0x1c],
315 #[doc = "0xf30 - CCU FANOUT CLOCK GATE Register"]
316 pub ccu_fan_gate: crate::Reg<ccu_fan_gate::CCU_FAN_GATE_SPEC>,
317 #[doc = "0xf34 - CLK27M FANOUT Register"]
318 pub clk27m_fan: crate::Reg<clk27m_fan::CLK27M_FAN_SPEC>,
319 #[doc = "0xf38 - PCLK FANOUT Register"]
320 pub pclk_fan: crate::Reg<pclk_fan::PCLK_FAN_SPEC>,
321 #[doc = "0xf3c - CCU FANOUT Register"]
322 pub ccu_fan: crate::Reg<ccu_fan::CCU_FAN_SPEC>,
323}
324#[doc = "PLL_CPU_CTRL register accessor: an alias for `Reg<PLL_CPU_CTRL_SPEC>`"]
325pub type PLL_CPU_CTRL = crate::Reg<pll_cpu_ctrl::PLL_CPU_CTRL_SPEC>;
326#[doc = "PLL_CPU Control Register"]
327pub mod pll_cpu_ctrl;
328#[doc = "PLL_DDR_CTRL register accessor: an alias for `Reg<PLL_DDR_CTRL_SPEC>`"]
329pub type PLL_DDR_CTRL = crate::Reg<pll_ddr_ctrl::PLL_DDR_CTRL_SPEC>;
330#[doc = "PLL_DDR Control Register"]
331pub mod pll_ddr_ctrl;
332#[doc = "PLL_PERI_CTRL register accessor: an alias for `Reg<PLL_PERI_CTRL_SPEC>`"]
333pub type PLL_PERI_CTRL = crate::Reg<pll_peri_ctrl::PLL_PERI_CTRL_SPEC>;
334#[doc = "PLL_PERI Control Register"]
335pub mod pll_peri_ctrl;
336#[doc = "PLL_VIDEO0_CTRL register accessor: an alias for `Reg<PLL_VIDEO0_CTRL_SPEC>`"]
337pub type PLL_VIDEO0_CTRL = crate::Reg<pll_video0_ctrl::PLL_VIDEO0_CTRL_SPEC>;
338#[doc = "PLL_VIDEO0 Control Register"]
339pub mod pll_video0_ctrl;
340#[doc = "PLL_VIDEO1_CTRL register accessor: an alias for `Reg<PLL_VIDEO1_CTRL_SPEC>`"]
341pub type PLL_VIDEO1_CTRL = crate::Reg<pll_video1_ctrl::PLL_VIDEO1_CTRL_SPEC>;
342#[doc = "PLL_VIDEO1 Control Register"]
343pub mod pll_video1_ctrl;
344#[doc = "PLL_VE_CTRL register accessor: an alias for `Reg<PLL_VE_CTRL_SPEC>`"]
345pub type PLL_VE_CTRL = crate::Reg<pll_ve_ctrl::PLL_VE_CTRL_SPEC>;
346#[doc = "PLL_VE Control Register"]
347pub mod pll_ve_ctrl;
348#[doc = "PLL_AUDIO0_CTRL register accessor: an alias for `Reg<PLL_AUDIO0_CTRL_SPEC>`"]
349pub type PLL_AUDIO0_CTRL = crate::Reg<pll_audio0_ctrl::PLL_AUDIO0_CTRL_SPEC>;
350#[doc = "PLL_AUDIO0 Control Register"]
351pub mod pll_audio0_ctrl;
352#[doc = "PLL_AUDIO1_CTRL register accessor: an alias for `Reg<PLL_AUDIO1_CTRL_SPEC>`"]
353pub type PLL_AUDIO1_CTRL = crate::Reg<pll_audio1_ctrl::PLL_AUDIO1_CTRL_SPEC>;
354#[doc = "PLL_AUDIO1 Control Register"]
355pub mod pll_audio1_ctrl;
356#[doc = "PLL_DDR_PAT0_CTRL register accessor: an alias for `Reg<PLL_DDR_PAT0_CTRL_SPEC>`"]
357pub type PLL_DDR_PAT0_CTRL = crate::Reg<pll_ddr_pat0_ctrl::PLL_DDR_PAT0_CTRL_SPEC>;
358#[doc = "PLL_DDR Pattern0 Control Register"]
359pub mod pll_ddr_pat0_ctrl;
360#[doc = "PLL_DDR_PAT1_CTRL register accessor: an alias for `Reg<PLL_DDR_PAT1_CTRL_SPEC>`"]
361pub type PLL_DDR_PAT1_CTRL = crate::Reg<pll_ddr_pat1_ctrl::PLL_DDR_PAT1_CTRL_SPEC>;
362#[doc = "PLL_DDR Pattern1 Control Register"]
363pub mod pll_ddr_pat1_ctrl;
364#[doc = "PLL_PERI_PAT0_CTRL register accessor: an alias for `Reg<PLL_PERI_PAT0_CTRL_SPEC>`"]
365pub type PLL_PERI_PAT0_CTRL = crate::Reg<pll_peri_pat0_ctrl::PLL_PERI_PAT0_CTRL_SPEC>;
366#[doc = "PLL_PERI Pattern0 Control Register"]
367pub mod pll_peri_pat0_ctrl;
368#[doc = "PLL_PERI_PAT1_CTRL register accessor: an alias for `Reg<PLL_PERI_PAT1_CTRL_SPEC>`"]
369pub type PLL_PERI_PAT1_CTRL = crate::Reg<pll_peri_pat1_ctrl::PLL_PERI_PAT1_CTRL_SPEC>;
370#[doc = "PLL_PERI Pattern1 Control Register"]
371pub mod pll_peri_pat1_ctrl;
372#[doc = "PLL_VIDEO0_PAT0_CTRL register accessor: an alias for `Reg<PLL_VIDEO0_PAT0_CTRL_SPEC>`"]
373pub type PLL_VIDEO0_PAT0_CTRL = crate::Reg<pll_video0_pat0_ctrl::PLL_VIDEO0_PAT0_CTRL_SPEC>;
374#[doc = "PLL_VIDEO0 Pattern0 Control Register"]
375pub mod pll_video0_pat0_ctrl;
376#[doc = "PLL_VIDEO0_PAT1_CTRL register accessor: an alias for `Reg<PLL_VIDEO0_PAT1_CTRL_SPEC>`"]
377pub type PLL_VIDEO0_PAT1_CTRL = crate::Reg<pll_video0_pat1_ctrl::PLL_VIDEO0_PAT1_CTRL_SPEC>;
378#[doc = "PLL_VIDEO0 Pattern1 Control Register"]
379pub mod pll_video0_pat1_ctrl;
380#[doc = "PLL_VIDEO1_PAT0_CTRL register accessor: an alias for `Reg<PLL_VIDEO1_PAT0_CTRL_SPEC>`"]
381pub type PLL_VIDEO1_PAT0_CTRL = crate::Reg<pll_video1_pat0_ctrl::PLL_VIDEO1_PAT0_CTRL_SPEC>;
382#[doc = "PLL_VIDEO1 Pattern0 Control Register"]
383pub mod pll_video1_pat0_ctrl;
384#[doc = "PLL_VIDEO1_PAT1_CTRL register accessor: an alias for `Reg<PLL_VIDEO1_PAT1_CTRL_SPEC>`"]
385pub type PLL_VIDEO1_PAT1_CTRL = crate::Reg<pll_video1_pat1_ctrl::PLL_VIDEO1_PAT1_CTRL_SPEC>;
386#[doc = "PLL_VIDEO1 Pattern1 Control Register"]
387pub mod pll_video1_pat1_ctrl;
388#[doc = "PLL_VE_PAT0_CTRL register accessor: an alias for `Reg<PLL_VE_PAT0_CTRL_SPEC>`"]
389pub type PLL_VE_PAT0_CTRL = crate::Reg<pll_ve_pat0_ctrl::PLL_VE_PAT0_CTRL_SPEC>;
390#[doc = "PLL_VE Pattern0 Control Register"]
391pub mod pll_ve_pat0_ctrl;
392#[doc = "PLL_VE_PAT1_CTRL register accessor: an alias for `Reg<PLL_VE_PAT1_CTRL_SPEC>`"]
393pub type PLL_VE_PAT1_CTRL = crate::Reg<pll_ve_pat1_ctrl::PLL_VE_PAT1_CTRL_SPEC>;
394#[doc = "PLL_VE Pattern1 Control Register"]
395pub mod pll_ve_pat1_ctrl;
396#[doc = "PLL_AUDIO0_PAT0_CTRL register accessor: an alias for `Reg<PLL_AUDIO0_PAT0_CTRL_SPEC>`"]
397pub type PLL_AUDIO0_PAT0_CTRL = crate::Reg<pll_audio0_pat0_ctrl::PLL_AUDIO0_PAT0_CTRL_SPEC>;
398#[doc = "PLL_AUDIO0 Pattern0 Control Register"]
399pub mod pll_audio0_pat0_ctrl;
400#[doc = "PLL_AUDIO0_PAT1_CTRL register accessor: an alias for `Reg<PLL_AUDIO0_PAT1_CTRL_SPEC>`"]
401pub type PLL_AUDIO0_PAT1_CTRL = crate::Reg<pll_audio0_pat1_ctrl::PLL_AUDIO0_PAT1_CTRL_SPEC>;
402#[doc = "PLL_AUDIO0 Pattern1 Control Register"]
403pub mod pll_audio0_pat1_ctrl;
404#[doc = "PLL_AUDIO1_PAT0_CTRL register accessor: an alias for `Reg<PLL_AUDIO1_PAT0_CTRL_SPEC>`"]
405pub type PLL_AUDIO1_PAT0_CTRL = crate::Reg<pll_audio1_pat0_ctrl::PLL_AUDIO1_PAT0_CTRL_SPEC>;
406#[doc = "PLL_AUDIO1 Pattern0 Control Register"]
407pub mod pll_audio1_pat0_ctrl;
408#[doc = "PLL_AUDIO1_PAT1_CTRL register accessor: an alias for `Reg<PLL_AUDIO1_PAT1_CTRL_SPEC>`"]
409pub type PLL_AUDIO1_PAT1_CTRL = crate::Reg<pll_audio1_pat1_ctrl::PLL_AUDIO1_PAT1_CTRL_SPEC>;
410#[doc = "PLL_AUDIO1 Pattern1 Control Register"]
411pub mod pll_audio1_pat1_ctrl;
412#[doc = "PLL_CPU_BIAS register accessor: an alias for `Reg<PLL_CPU_BIAS_SPEC>`"]
413pub type PLL_CPU_BIAS = crate::Reg<pll_cpu_bias::PLL_CPU_BIAS_SPEC>;
414#[doc = "PLL_CPU Bias Register"]
415pub mod pll_cpu_bias;
416#[doc = "PLL_DDR_BIAS register accessor: an alias for `Reg<PLL_DDR_BIAS_SPEC>`"]
417pub type PLL_DDR_BIAS = crate::Reg<pll_ddr_bias::PLL_DDR_BIAS_SPEC>;
418#[doc = "PLL_DDR Bias Register"]
419pub mod pll_ddr_bias;
420#[doc = "PLL_PERI_BIAS register accessor: an alias for `Reg<PLL_PERI_BIAS_SPEC>`"]
421pub type PLL_PERI_BIAS = crate::Reg<pll_peri_bias::PLL_PERI_BIAS_SPEC>;
422#[doc = "PLL_PERI Bias Register"]
423pub mod pll_peri_bias;
424#[doc = "PLL_VIDEO0_BIAS register accessor: an alias for `Reg<PLL_VIDEO0_BIAS_SPEC>`"]
425pub type PLL_VIDEO0_BIAS = crate::Reg<pll_video0_bias::PLL_VIDEO0_BIAS_SPEC>;
426#[doc = "PLL_VIDEO0 Bias Register"]
427pub mod pll_video0_bias;
428#[doc = "PLL_VIDEO1_BIAS register accessor: an alias for `Reg<PLL_VIDEO1_BIAS_SPEC>`"]
429pub type PLL_VIDEO1_BIAS = crate::Reg<pll_video1_bias::PLL_VIDEO1_BIAS_SPEC>;
430#[doc = "PLL_VIDEO1 Bias Register"]
431pub mod pll_video1_bias;
432#[doc = "PLL_VE_BIAS register accessor: an alias for `Reg<PLL_VE_BIAS_SPEC>`"]
433pub type PLL_VE_BIAS = crate::Reg<pll_ve_bias::PLL_VE_BIAS_SPEC>;
434#[doc = "PLL_VE Bias Register"]
435pub mod pll_ve_bias;
436#[doc = "PLL_AUDIO0_BIAS register accessor: an alias for `Reg<PLL_AUDIO0_BIAS_SPEC>`"]
437pub type PLL_AUDIO0_BIAS = crate::Reg<pll_audio0_bias::PLL_AUDIO0_BIAS_SPEC>;
438#[doc = "PLL_AUDIO0 Bias Register"]
439pub mod pll_audio0_bias;
440#[doc = "PLL_AUDIO1_BIAS register accessor: an alias for `Reg<PLL_AUDIO1_BIAS_SPEC>`"]
441pub type PLL_AUDIO1_BIAS = crate::Reg<pll_audio1_bias::PLL_AUDIO1_BIAS_SPEC>;
442#[doc = "PLL_AUDIO1 Bias Register"]
443pub mod pll_audio1_bias;
444#[doc = "PLL_CPU_TUN register accessor: an alias for `Reg<PLL_CPU_TUN_SPEC>`"]
445pub type PLL_CPU_TUN = crate::Reg<pll_cpu_tun::PLL_CPU_TUN_SPEC>;
446#[doc = "PLL_CPU Tuning Register"]
447pub mod pll_cpu_tun;
448#[doc = "CPU_AXI_CFG register accessor: an alias for `Reg<CPU_AXI_CFG_SPEC>`"]
449pub type CPU_AXI_CFG = crate::Reg<cpu_axi_cfg::CPU_AXI_CFG_SPEC>;
450#[doc = "CPU_AXI Configuration Register"]
451pub mod cpu_axi_cfg;
452#[doc = "CPU_GATING register accessor: an alias for `Reg<CPU_GATING_SPEC>`"]
453pub type CPU_GATING = crate::Reg<cpu_gating::CPU_GATING_SPEC>;
454#[doc = "CPU_GATING Configuration Register"]
455pub mod cpu_gating;
456#[doc = "PSI_CLK register accessor: an alias for `Reg<PSI_CLK_SPEC>`"]
457pub type PSI_CLK = crate::Reg<psi_clk::PSI_CLK_SPEC>;
458#[doc = "PSI Clock Register"]
459pub mod psi_clk;
460#[doc = "APB_CLK register accessor: an alias for `Reg<APB_CLK_SPEC>`"]
461pub type APB_CLK = crate::Reg<apb_clk::APB_CLK_SPEC>;
462#[doc = "APB Clock Register"]
463pub mod apb_clk;
464#[doc = "MBUS_CLK register accessor: an alias for `Reg<MBUS_CLK_SPEC>`"]
465pub type MBUS_CLK = crate::Reg<mbus_clk::MBUS_CLK_SPEC>;
466#[doc = "MBUS Clock Register"]
467pub mod mbus_clk;
468#[doc = "DE_CLK register accessor: an alias for `Reg<DE_CLK_SPEC>`"]
469pub type DE_CLK = crate::Reg<de_clk::DE_CLK_SPEC>;
470#[doc = "DE Clock Register"]
471pub mod de_clk;
472#[doc = "DE_BGR register accessor: an alias for `Reg<DE_BGR_SPEC>`"]
473pub type DE_BGR = crate::Reg<de_bgr::DE_BGR_SPEC>;
474#[doc = "DE Bus Gating Reset Register"]
475pub mod de_bgr;
476#[doc = "DI_CLK register accessor: an alias for `Reg<DI_CLK_SPEC>`"]
477pub type DI_CLK = crate::Reg<di_clk::DI_CLK_SPEC>;
478#[doc = "DI Clock Register"]
479pub mod di_clk;
480#[doc = "DI_BGR register accessor: an alias for `Reg<DI_BGR_SPEC>`"]
481pub type DI_BGR = crate::Reg<di_bgr::DI_BGR_SPEC>;
482#[doc = "DI Bus Gating Reset Register"]
483pub mod di_bgr;
484#[doc = "G2D_CLK register accessor: an alias for `Reg<G2D_CLK_SPEC>`"]
485pub type G2D_CLK = crate::Reg<g2d_clk::G2D_CLK_SPEC>;
486#[doc = "G2D Clock Register"]
487pub mod g2d_clk;
488#[doc = "G2D_BGR register accessor: an alias for `Reg<G2D_BGR_SPEC>`"]
489pub type G2D_BGR = crate::Reg<g2d_bgr::G2D_BGR_SPEC>;
490#[doc = "G2D Bus Gating Reset Register"]
491pub mod g2d_bgr;
492#[doc = "CE_CLK register accessor: an alias for `Reg<CE_CLK_SPEC>`"]
493pub type CE_CLK = crate::Reg<ce_clk::CE_CLK_SPEC>;
494#[doc = "CE Clock Register"]
495pub mod ce_clk;
496#[doc = "CE_BGR register accessor: an alias for `Reg<CE_BGR_SPEC>`"]
497pub type CE_BGR = crate::Reg<ce_bgr::CE_BGR_SPEC>;
498#[doc = "CE Bus Gating Reset Register"]
499pub mod ce_bgr;
500#[doc = "VE_CLK register accessor: an alias for `Reg<VE_CLK_SPEC>`"]
501pub type VE_CLK = crate::Reg<ve_clk::VE_CLK_SPEC>;
502#[doc = "VE Clock Register"]
503pub mod ve_clk;
504#[doc = "VE_BGR register accessor: an alias for `Reg<VE_BGR_SPEC>`"]
505pub type VE_BGR = crate::Reg<ve_bgr::VE_BGR_SPEC>;
506#[doc = "VE Bus Gating Reset Register"]
507pub mod ve_bgr;
508#[doc = "DMA_BGR register accessor: an alias for `Reg<DMA_BGR_SPEC>`"]
509pub type DMA_BGR = crate::Reg<dma_bgr::DMA_BGR_SPEC>;
510#[doc = "DMA Bus Gating Reset Register"]
511pub mod dma_bgr;
512#[doc = "MSGBOX_BGR register accessor: an alias for `Reg<MSGBOX_BGR_SPEC>`"]
513pub type MSGBOX_BGR = crate::Reg<msgbox_bgr::MSGBOX_BGR_SPEC>;
514#[doc = "MSGBOX Bus Gating Reset Register"]
515pub mod msgbox_bgr;
516#[doc = "SPINLOCK_BGR register accessor: an alias for `Reg<SPINLOCK_BGR_SPEC>`"]
517pub type SPINLOCK_BGR = crate::Reg<spinlock_bgr::SPINLOCK_BGR_SPEC>;
518#[doc = "SPINLOCK Bus Gating Reset Register"]
519pub mod spinlock_bgr;
520#[doc = "HSTIMER_BGR register accessor: an alias for `Reg<HSTIMER_BGR_SPEC>`"]
521pub type HSTIMER_BGR = crate::Reg<hstimer_bgr::HSTIMER_BGR_SPEC>;
522#[doc = "HSTIMER Bus Gating Reset Register"]
523pub mod hstimer_bgr;
524#[doc = "AVS_CLK register accessor: an alias for `Reg<AVS_CLK_SPEC>`"]
525pub type AVS_CLK = crate::Reg<avs_clk::AVS_CLK_SPEC>;
526#[doc = "AVS Clock Register"]
527pub mod avs_clk;
528#[doc = "DBGSYS_BGR register accessor: an alias for `Reg<DBGSYS_BGR_SPEC>`"]
529pub type DBGSYS_BGR = crate::Reg<dbgsys_bgr::DBGSYS_BGR_SPEC>;
530#[doc = "DBGSYS Bus Gating Reset Register"]
531pub mod dbgsys_bgr;
532#[doc = "PWM_BGR register accessor: an alias for `Reg<PWM_BGR_SPEC>`"]
533pub type PWM_BGR = crate::Reg<pwm_bgr::PWM_BGR_SPEC>;
534#[doc = "PWM Bus Gating Reset Register"]
535pub mod pwm_bgr;
536#[doc = "IOMMU_BGR register accessor: an alias for `Reg<IOMMU_BGR_SPEC>`"]
537pub type IOMMU_BGR = crate::Reg<iommu_bgr::IOMMU_BGR_SPEC>;
538#[doc = "IOMMU Bus Gating Reset Register"]
539pub mod iommu_bgr;
540#[doc = "DRAM_CLK register accessor: an alias for `Reg<DRAM_CLK_SPEC>`"]
541pub type DRAM_CLK = crate::Reg<dram_clk::DRAM_CLK_SPEC>;
542#[doc = "DRAM Clock Register"]
543pub mod dram_clk;
544#[doc = "MBUS_MAT_CLK_GATING register accessor: an alias for `Reg<MBUS_MAT_CLK_GATING_SPEC>`"]
545pub type MBUS_MAT_CLK_GATING = crate::Reg<mbus_mat_clk_gating::MBUS_MAT_CLK_GATING_SPEC>;
546#[doc = "MBUS Master Clock Gating Register"]
547pub mod mbus_mat_clk_gating;
548#[doc = "DRAM_BGR register accessor: an alias for `Reg<DRAM_BGR_SPEC>`"]
549pub type DRAM_BGR = crate::Reg<dram_bgr::DRAM_BGR_SPEC>;
550#[doc = "DRAM Bus Gating Reset Register"]
551pub mod dram_bgr;
552#[doc = "SMHC0_CLK register accessor: an alias for `Reg<SMHC0_CLK_SPEC>`"]
553pub type SMHC0_CLK = crate::Reg<smhc0_clk::SMHC0_CLK_SPEC>;
554#[doc = "SMHC0 Clock Register"]
555pub mod smhc0_clk;
556#[doc = "SMHC1_CLK register accessor: an alias for `Reg<SMHC1_CLK_SPEC>`"]
557pub type SMHC1_CLK = crate::Reg<smhc1_clk::SMHC1_CLK_SPEC>;
558#[doc = "SMHC1 Clock Register"]
559pub mod smhc1_clk;
560#[doc = "SMHC2_CLK register accessor: an alias for `Reg<SMHC2_CLK_SPEC>`"]
561pub type SMHC2_CLK = crate::Reg<smhc2_clk::SMHC2_CLK_SPEC>;
562#[doc = "SMHC2 Clock Register"]
563pub mod smhc2_clk;
564#[doc = "SMHC_BGR register accessor: an alias for `Reg<SMHC_BGR_SPEC>`"]
565pub type SMHC_BGR = crate::Reg<smhc_bgr::SMHC_BGR_SPEC>;
566#[doc = "SMHC Bus Gating Reset Register"]
567pub mod smhc_bgr;
568#[doc = "UART_BGR register accessor: an alias for `Reg<UART_BGR_SPEC>`"]
569pub type UART_BGR = crate::Reg<uart_bgr::UART_BGR_SPEC>;
570#[doc = "UART Bus Gating Reset Register"]
571pub mod uart_bgr;
572#[doc = "TWI_BGR register accessor: an alias for `Reg<TWI_BGR_SPEC>`"]
573pub type TWI_BGR = crate::Reg<twi_bgr::TWI_BGR_SPEC>;
574#[doc = "TWI Bus Gating Reset Register"]
575pub mod twi_bgr;
576#[doc = "SPI0_CLK register accessor: an alias for `Reg<SPI0_CLK_SPEC>`"]
577pub type SPI0_CLK = crate::Reg<spi0_clk::SPI0_CLK_SPEC>;
578#[doc = "SPI0 Clock Register"]
579pub mod spi0_clk;
580#[doc = "SPI1_CLK register accessor: an alias for `Reg<SPI1_CLK_SPEC>`"]
581pub type SPI1_CLK = crate::Reg<spi1_clk::SPI1_CLK_SPEC>;
582#[doc = "SPI1 Clock Register"]
583pub mod spi1_clk;
584#[doc = "SPI_BGR register accessor: an alias for `Reg<SPI_BGR_SPEC>`"]
585pub type SPI_BGR = crate::Reg<spi_bgr::SPI_BGR_SPEC>;
586#[doc = "SPI Bus Gating Reset Register"]
587pub mod spi_bgr;
588#[doc = "EMAC_25M_CLK register accessor: an alias for `Reg<EMAC_25M_CLK_SPEC>`"]
589pub type EMAC_25M_CLK = crate::Reg<emac_25m_clk::EMAC_25M_CLK_SPEC>;
590#[doc = "EMAC_25M Clock Register"]
591pub mod emac_25m_clk;
592#[doc = "EMAC_BGR register accessor: an alias for `Reg<EMAC_BGR_SPEC>`"]
593pub type EMAC_BGR = crate::Reg<emac_bgr::EMAC_BGR_SPEC>;
594#[doc = "EMAC Bus Gating Reset Register"]
595pub mod emac_bgr;
596#[doc = "IRTX_CLK register accessor: an alias for `Reg<IRTX_CLK_SPEC>`"]
597pub type IRTX_CLK = crate::Reg<irtx_clk::IRTX_CLK_SPEC>;
598#[doc = "IRTX Clock Register"]
599pub mod irtx_clk;
600#[doc = "IRTX_BGR register accessor: an alias for `Reg<IRTX_BGR_SPEC>`"]
601pub type IRTX_BGR = crate::Reg<irtx_bgr::IRTX_BGR_SPEC>;
602#[doc = "IRTX Bus Gating Reset Register"]
603pub mod irtx_bgr;
604#[doc = "GPADC_BGR register accessor: an alias for `Reg<GPADC_BGR_SPEC>`"]
605pub type GPADC_BGR = crate::Reg<gpadc_bgr::GPADC_BGR_SPEC>;
606#[doc = "GPADC Bus Gating Reset Register"]
607pub mod gpadc_bgr;
608#[doc = "THS_BGR register accessor: an alias for `Reg<THS_BGR_SPEC>`"]
609pub type THS_BGR = crate::Reg<ths_bgr::THS_BGR_SPEC>;
610#[doc = "THS Bus Gating Reset Register"]
611pub mod ths_bgr;
612#[doc = "I2S_CLK register accessor: an alias for `Reg<I2S_CLK_SPEC>`"]
613pub type I2S_CLK = crate::Reg<i2s_clk::I2S_CLK_SPEC>;
614#[doc = "I2S Clock Register"]
615pub mod i2s_clk;
616#[doc = "I2S2_ASRC_CLK register accessor: an alias for `Reg<I2S2_ASRC_CLK_SPEC>`"]
617pub type I2S2_ASRC_CLK = crate::Reg<i2s2_asrc_clk::I2S2_ASRC_CLK_SPEC>;
618#[doc = "I2S2_ASRC Clock Register"]
619pub mod i2s2_asrc_clk;
620#[doc = "I2S_BGR register accessor: an alias for `Reg<I2S_BGR_SPEC>`"]
621pub type I2S_BGR = crate::Reg<i2s_bgr::I2S_BGR_SPEC>;
622#[doc = "I2S Bus Gating Reset Register"]
623pub mod i2s_bgr;
624#[doc = "OWA_TX_CLK register accessor: an alias for `Reg<OWA_TX_CLK_SPEC>`"]
625pub type OWA_TX_CLK = crate::Reg<owa_tx_clk::OWA_TX_CLK_SPEC>;
626#[doc = "OWA_TX Clock Register"]
627pub mod owa_tx_clk;
628#[doc = "OWA_RX_CLK register accessor: an alias for `Reg<OWA_RX_CLK_SPEC>`"]
629pub type OWA_RX_CLK = crate::Reg<owa_rx_clk::OWA_RX_CLK_SPEC>;
630#[doc = "OWA_RX Clock Register"]
631pub mod owa_rx_clk;
632#[doc = "OWA_BGR register accessor: an alias for `Reg<OWA_BGR_SPEC>`"]
633pub type OWA_BGR = crate::Reg<owa_bgr::OWA_BGR_SPEC>;
634#[doc = "OWA Bus Gating Reset Register"]
635pub mod owa_bgr;
636#[doc = "DMIC_CLK register accessor: an alias for `Reg<DMIC_CLK_SPEC>`"]
637pub type DMIC_CLK = crate::Reg<dmic_clk::DMIC_CLK_SPEC>;
638#[doc = "DMIC Clock Register"]
639pub mod dmic_clk;
640#[doc = "DMIC_BGR register accessor: an alias for `Reg<DMIC_BGR_SPEC>`"]
641pub type DMIC_BGR = crate::Reg<dmic_bgr::DMIC_BGR_SPEC>;
642#[doc = "DMIC Bus Gating Reset Register"]
643pub mod dmic_bgr;
644#[doc = "AUDIO_CODEC_DAC_CLK register accessor: an alias for `Reg<AUDIO_CODEC_DAC_CLK_SPEC>`"]
645pub type AUDIO_CODEC_DAC_CLK = crate::Reg<audio_codec_dac_clk::AUDIO_CODEC_DAC_CLK_SPEC>;
646#[doc = "AUDIO_CODEC_DAC Clock Register"]
647pub mod audio_codec_dac_clk;
648#[doc = "AUDIO_CODEC_ADC_CLK register accessor: an alias for `Reg<AUDIO_CODEC_ADC_CLK_SPEC>`"]
649pub type AUDIO_CODEC_ADC_CLK = crate::Reg<audio_codec_adc_clk::AUDIO_CODEC_ADC_CLK_SPEC>;
650#[doc = "AUDIO_CODEC_ADC Clock Register"]
651pub mod audio_codec_adc_clk;
652#[doc = "AUDIO_CODEC_BGR register accessor: an alias for `Reg<AUDIO_CODEC_BGR_SPEC>`"]
653pub type AUDIO_CODEC_BGR = crate::Reg<audio_codec_bgr::AUDIO_CODEC_BGR_SPEC>;
654#[doc = "AUDIO_CODEC Bus Gating Reset Register"]
655pub mod audio_codec_bgr;
656#[doc = "USB0_CLK register accessor: an alias for `Reg<USB0_CLK_SPEC>`"]
657pub type USB0_CLK = crate::Reg<usb0_clk::USB0_CLK_SPEC>;
658#[doc = "USB0 Clock Register"]
659pub mod usb0_clk;
660#[doc = "USB1_CLK register accessor: an alias for `Reg<USB1_CLK_SPEC>`"]
661pub type USB1_CLK = crate::Reg<usb1_clk::USB1_CLK_SPEC>;
662#[doc = "USB1 Clock Register"]
663pub mod usb1_clk;
664#[doc = "USB_BGR register accessor: an alias for `Reg<USB_BGR_SPEC>`"]
665pub type USB_BGR = crate::Reg<usb_bgr::USB_BGR_SPEC>;
666#[doc = "USB Bus Gating Reset Register"]
667pub mod usb_bgr;
668#[doc = "LRADC_BGR register accessor: an alias for `Reg<LRADC_BGR_SPEC>`"]
669pub type LRADC_BGR = crate::Reg<lradc_bgr::LRADC_BGR_SPEC>;
670#[doc = "LRADC Bus Gating Reset Register"]
671pub mod lradc_bgr;
672#[doc = "DPSS_TOP_BGR register accessor: an alias for `Reg<DPSS_TOP_BGR_SPEC>`"]
673pub type DPSS_TOP_BGR = crate::Reg<dpss_top_bgr::DPSS_TOP_BGR_SPEC>;
674#[doc = "DPSS_TOP Bus Gating Reset Register"]
675pub mod dpss_top_bgr;
676#[doc = "DSI_CLK register accessor: an alias for `Reg<DSI_CLK_SPEC>`"]
677pub type DSI_CLK = crate::Reg<dsi_clk::DSI_CLK_SPEC>;
678#[doc = "DSI Clock Register"]
679pub mod dsi_clk;
680#[doc = "DSI_BGR register accessor: an alias for `Reg<DSI_BGR_SPEC>`"]
681pub type DSI_BGR = crate::Reg<dsi_bgr::DSI_BGR_SPEC>;
682#[doc = "DSI Bus Gating Reset Register"]
683pub mod dsi_bgr;
684#[doc = "TCONLCD_CLK register accessor: an alias for `Reg<TCONLCD_CLK_SPEC>`"]
685pub type TCONLCD_CLK = crate::Reg<tconlcd_clk::TCONLCD_CLK_SPEC>;
686#[doc = "TCONLCD Clock Register"]
687pub mod tconlcd_clk;
688#[doc = "TCONLCD_BGR register accessor: an alias for `Reg<TCONLCD_BGR_SPEC>`"]
689pub type TCONLCD_BGR = crate::Reg<tconlcd_bgr::TCONLCD_BGR_SPEC>;
690#[doc = "TCONLCD Bus Gating Reset Register"]
691pub mod tconlcd_bgr;
692#[doc = "TCONTV_CLK register accessor: an alias for `Reg<TCONTV_CLK_SPEC>`"]
693pub type TCONTV_CLK = crate::Reg<tcontv_clk::TCONTV_CLK_SPEC>;
694#[doc = "TCONTV Clock Register"]
695pub mod tcontv_clk;
696#[doc = "TCONTV_BGR register accessor: an alias for `Reg<TCONTV_BGR_SPEC>`"]
697pub type TCONTV_BGR = crate::Reg<tcontv_bgr::TCONTV_BGR_SPEC>;
698#[doc = "TCONTV Bus Gating Reset Register"]
699pub mod tcontv_bgr;
700#[doc = "LVDS_BGR register accessor: an alias for `Reg<LVDS_BGR_SPEC>`"]
701pub type LVDS_BGR = crate::Reg<lvds_bgr::LVDS_BGR_SPEC>;
702#[doc = "LVDS Bus Gating Reset Register"]
703pub mod lvds_bgr;
704#[doc = "TVE_CLK register accessor: an alias for `Reg<TVE_CLK_SPEC>`"]
705pub type TVE_CLK = crate::Reg<tve_clk::TVE_CLK_SPEC>;
706#[doc = "TVE Clock Register"]
707pub mod tve_clk;
708#[doc = "TVE_BGR register accessor: an alias for `Reg<TVE_BGR_SPEC>`"]
709pub type TVE_BGR = crate::Reg<tve_bgr::TVE_BGR_SPEC>;
710#[doc = "TVE Bus Gating Reset Register"]
711pub mod tve_bgr;
712#[doc = "TVD_CLK register accessor: an alias for `Reg<TVD_CLK_SPEC>`"]
713pub type TVD_CLK = crate::Reg<tvd_clk::TVD_CLK_SPEC>;
714#[doc = "TVD Clock Register"]
715pub mod tvd_clk;
716#[doc = "TVD_BGR register accessor: an alias for `Reg<TVD_BGR_SPEC>`"]
717pub type TVD_BGR = crate::Reg<tvd_bgr::TVD_BGR_SPEC>;
718#[doc = "TVD Bus Gating Reset Register"]
719pub mod tvd_bgr;
720#[doc = "LEDC_CLK register accessor: an alias for `Reg<LEDC_CLK_SPEC>`"]
721pub type LEDC_CLK = crate::Reg<ledc_clk::LEDC_CLK_SPEC>;
722#[doc = "LEDC Clock Register"]
723pub mod ledc_clk;
724#[doc = "LEDC_BGR register accessor: an alias for `Reg<LEDC_BGR_SPEC>`"]
725pub type LEDC_BGR = crate::Reg<ledc_bgr::LEDC_BGR_SPEC>;
726#[doc = "LEDC Bus Gating Reset Register"]
727pub mod ledc_bgr;
728#[doc = "CSI_CLK register accessor: an alias for `Reg<CSI_CLK_SPEC>`"]
729pub type CSI_CLK = crate::Reg<csi_clk::CSI_CLK_SPEC>;
730#[doc = "CSI Clock Register"]
731pub mod csi_clk;
732#[doc = "CSI_MASTER_CLK register accessor: an alias for `Reg<CSI_MASTER_CLK_SPEC>`"]
733pub type CSI_MASTER_CLK = crate::Reg<csi_master_clk::CSI_MASTER_CLK_SPEC>;
734#[doc = "CSI Master Clock Register"]
735pub mod csi_master_clk;
736#[doc = "CSI_BGR register accessor: an alias for `Reg<CSI_BGR_SPEC>`"]
737pub type CSI_BGR = crate::Reg<csi_bgr::CSI_BGR_SPEC>;
738#[doc = "CSI Bus Gating Reset Register"]
739pub mod csi_bgr;
740#[doc = "TPADC_CLK register accessor: an alias for `Reg<TPADC_CLK_SPEC>`"]
741pub type TPADC_CLK = crate::Reg<tpadc_clk::TPADC_CLK_SPEC>;
742#[doc = "TPADC Clock Register"]
743pub mod tpadc_clk;
744#[doc = "TPADC_BGR register accessor: an alias for `Reg<TPADC_BGR_SPEC>`"]
745pub type TPADC_BGR = crate::Reg<tpadc_bgr::TPADC_BGR_SPEC>;
746#[doc = "TPADC Bus Gating Reset Register"]
747pub mod tpadc_bgr;
748#[doc = "DSP_CLK register accessor: an alias for `Reg<DSP_CLK_SPEC>`"]
749pub type DSP_CLK = crate::Reg<dsp_clk::DSP_CLK_SPEC>;
750#[doc = "DSP Clock Register"]
751pub mod dsp_clk;
752#[doc = "DSP_BGR register accessor: an alias for `Reg<DSP_BGR_SPEC>`"]
753pub type DSP_BGR = crate::Reg<dsp_bgr::DSP_BGR_SPEC>;
754#[doc = "DSP Bus Gating Reset Register"]
755pub mod dsp_bgr;
756#[doc = "RISCV_CLK register accessor: an alias for `Reg<RISCV_CLK_SPEC>`"]
757pub type RISCV_CLK = crate::Reg<riscv_clk::RISCV_CLK_SPEC>;
758#[doc = "RISC-V Clock Register"]
759pub mod riscv_clk;
760#[doc = "RISCV_GATING register accessor: an alias for `Reg<RISCV_GATING_SPEC>`"]
761pub type RISCV_GATING = crate::Reg<riscv_gating::RISCV_GATING_SPEC>;
762#[doc = "RISC-V GATING Configuration Register"]
763pub mod riscv_gating;
764#[doc = "RISCV_CFG_BGR register accessor: an alias for `Reg<RISCV_CFG_BGR_SPEC>`"]
765pub type RISCV_CFG_BGR = crate::Reg<riscv_cfg_bgr::RISCV_CFG_BGR_SPEC>;
766#[doc = "RISC-V_CFG Bus Gating Reset Register"]
767pub mod riscv_cfg_bgr;
768#[doc = "PLL_LOCK_DBG_CTRL register accessor: an alias for `Reg<PLL_LOCK_DBG_CTRL_SPEC>`"]
769pub type PLL_LOCK_DBG_CTRL = crate::Reg<pll_lock_dbg_ctrl::PLL_LOCK_DBG_CTRL_SPEC>;
770#[doc = "PLL Lock Debug Control Register"]
771pub mod pll_lock_dbg_ctrl;
772#[doc = "FRE_DET_CTRL register accessor: an alias for `Reg<FRE_DET_CTRL_SPEC>`"]
773pub type FRE_DET_CTRL = crate::Reg<fre_det_ctrl::FRE_DET_CTRL_SPEC>;
774#[doc = "Frequency Detect Control Register"]
775pub mod fre_det_ctrl;
776#[doc = "FRE_UP_LIM register accessor: an alias for `Reg<FRE_UP_LIM_SPEC>`"]
777pub type FRE_UP_LIM = crate::Reg<fre_up_lim::FRE_UP_LIM_SPEC>;
778#[doc = "Frequency Up Limit Register"]
779pub mod fre_up_lim;
780#[doc = "FRE_DOWN_LIM register accessor: an alias for `Reg<FRE_DOWN_LIM_SPEC>`"]
781pub type FRE_DOWN_LIM = crate::Reg<fre_down_lim::FRE_DOWN_LIM_SPEC>;
782#[doc = "Frequency Down Limit Register"]
783pub mod fre_down_lim;
784#[doc = "CCU_FAN_GATE register accessor: an alias for `Reg<CCU_FAN_GATE_SPEC>`"]
785pub type CCU_FAN_GATE = crate::Reg<ccu_fan_gate::CCU_FAN_GATE_SPEC>;
786#[doc = "CCU FANOUT CLOCK GATE Register"]
787pub mod ccu_fan_gate;
788#[doc = "CLK27M_FAN register accessor: an alias for `Reg<CLK27M_FAN_SPEC>`"]
789pub type CLK27M_FAN = crate::Reg<clk27m_fan::CLK27M_FAN_SPEC>;
790#[doc = "CLK27M FANOUT Register"]
791pub mod clk27m_fan;
792#[doc = "PCLK_FAN register accessor: an alias for `Reg<PCLK_FAN_SPEC>`"]
793pub type PCLK_FAN = crate::Reg<pclk_fan::PCLK_FAN_SPEC>;
794#[doc = "PCLK FANOUT Register"]
795pub mod pclk_fan;
796#[doc = "CCU_FAN register accessor: an alias for `Reg<CCU_FAN_SPEC>`"]
797pub type CCU_FAN = crate::Reg<ccu_fan::CCU_FAN_SPEC>;
798#[doc = "CCU FANOUT Register"]
799pub mod ccu_fan;