[−][src]Trait r3_port_riscv::TimerOptions

pub trait TimerOptions {
    pub const MTIME_PTR: usize;
    pub const MTIMECMP_PTR: usize;
    pub const RESET_MTIME: bool;
    pub const FREQUENCY: u64;
    pub const FREQUENCY_DENOMINATOR: u64;
    pub const HEADROOM: u32;
    pub const INTERRUPT_NUM: InterruptNum;
}

The options for use_timer!.

Associated Constants

pub const MTIME_PTR: usize[src]

The memory address of the mtime register.

pub const MTIMECMP_PTR: usize[src]

The memory address of the mtimecmp register.

pub const RESET_MTIME: bool[src]

When set to true, the driver clears the lower 32 bits of the mtime register on boot.

Disabling this might increase the runtime overhead of the driver. Nevertheless, the need to disable this might arise for numerous reasons including:

  • Updating the mtime register is not supported by QEMU at this time.

  • The mtime register might be shared with other harts and clearing it could confuse the code running in the other harts.

pub const FREQUENCY: u64[src]

The numerator of the effective timer clock rate of the dual timer.

pub const FREQUENCY_DENOMINATOR: u64[src]

The denominator of the effective timer clock rate of the dual timer. Defaults to 1.

pub const HEADROOM: u32[src]

The maximum permissible timer interrupt latency, measured in hardware timer cycles.

Defaults to min(FREQUENCY * 60 / FREQUENCY_DENOMINATOR, 0x40000000).

pub const INTERRUPT_NUM: InterruptNum[src]

The timer's interrupt number. Defaults to INTERRUPT_TIMER.

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Implementors

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