Module aarch64_encoding 

Operand-aware helpers for the AArch64 cset / csel / csinc / csinv / csneg family.

These pseudo-instructions all derive their result from a flag predicate plus one or two general-purpose registers. When r2SMT proves the predicate constant, the cs* instruction collapses to a deterministic data-movement form. The helpers in this module synthesize the equivalent textual assembly so BytePatcher::assemble can encode it (see ARM ARM Vol. C §C6.2 for the canonical reference encodings):

• cset → mov Rd, #imm (csinc Rd, RZR, RZR, !cond)
• csetm → mov Rd, #imm (csinv Rd, RZR, RZR, !cond)
• csel → mov Rd, Rn or Rm
• csinc → mov Rd, Rn or add Rd, Rm, #1
• csinv → mov Rd, Rn or mvn Rd, Rm
• csneg → mov Rd, Rn or neg Rd, Rm

The functions intentionally avoid hand-encoding instruction bytes: delegating to r2’s assembler (or to the in-memory test double’s add_assemble) keeps the encoding path identical to the replace_jcc_with_jmp strategy and avoids reimplementing the Armv8 MOV (register) / ADD (immediate) aliases by hand.

Constants

ZERO_REGISTER_W

Canonical “wide” zero register name for 32-bit views.

ZERO_REGISTER_X

Canonical “wide” zero register name. Returned by parse_xreg when the operand text is one of xzr / wzr.

Functions

add_imm

Assemble syntax for add Rd, Rs, #imm.

mov_imm

Assemble syntax for mov Rd, #imm (a MOVZ / MOVN alias).

mov_reg

Assemble syntax for mov Rd, Rs (the AArch64 register-move alias).

mvn_reg

Assemble syntax for mvn Rd, Rs (bitwise NOT — ORN Rd, RZR, Rs).

neg_reg

Assemble syntax for neg Rd, Rs (two’s-complement negation — SUB Rd, RZR, Rs).

parse_xreg

Parse a raw operand string into a canonical AArch64 GPR name.