quantrs2_sim/automatic_parallelization/
types.rs

1//! Auto-generated module
2//!
3//! 🤖 Generated with [SplitRS](https://github.com/cool-japan/splitrs)
4
5use quantrs2_circuit::builder::{Circuit, Simulator};
6use quantrs2_core::{gate::GateOp, qubit::QubitId};
7use serde::{Deserialize, Serialize};
8use std::collections::{BTreeMap, BTreeSet, HashMap, HashSet, VecDeque};
9use std::sync::{Arc, Barrier, Mutex, RwLock};
10use std::time::{Duration, Instant};
11use uuid::Uuid;
12
13/// Hardware-specific parallelization strategies
14#[derive(Debug, Clone, Copy, PartialEq, Eq)]
15pub enum HardwareStrategy {
16    /// Optimize for cache locality
17    CacheOptimized,
18    /// Optimize for SIMD vectorization
19    SIMDOptimized,
20    /// NUMA-aware task distribution
21    NUMAAware,
22    /// Offload to GPU
23    GPUOffload,
24    /// Hybrid approach combining multiple optimizations
25    Hybrid,
26}
27/// Types of optimization recommendations
28#[derive(Debug, Clone, Copy, PartialEq, Eq)]
29pub enum RecommendationType {
30    /// Gate reordering for better parallelism
31    GateReordering,
32    /// Circuit decomposition
33    CircuitDecomposition,
34    /// Resource allocation adjustment
35    ResourceAllocation,
36    /// Strategy change recommendation
37    StrategyChange,
38    /// Hardware configuration
39    HardwareConfiguration,
40}
41/// ML features extracted from circuits for parallelization prediction
42#[derive(Debug, Clone)]
43pub struct MLFeatures {
44    /// Number of gates in the circuit
45    pub num_gates: usize,
46    /// Number of qubits in the circuit
47    pub num_qubits: usize,
48    /// Circuit depth (critical path length)
49    pub circuit_depth: usize,
50    /// Average gate connectivity
51    pub avg_connectivity: f64,
52    /// Parallelism factor (ratio of independent gates)
53    pub parallelism_factor: f64,
54    /// Gate type distribution
55    pub gate_distribution: HashMap<String, usize>,
56    /// Entanglement complexity score
57    pub entanglement_score: f64,
58    /// Dependency density (edges per gate)
59    pub dependency_density: f64,
60}
61/// Hardware characteristics for hardware-aware parallelization
62#[derive(Debug, Clone)]
63pub struct HardwareCharacteristics {
64    /// Number of available CPU cores
65    pub num_cores: usize,
66    /// L1 cache size per core (bytes)
67    pub l1_cache_size: usize,
68    /// L2 cache size per core (bytes)
69    pub l2_cache_size: usize,
70    /// L3 cache size (bytes)
71    pub l3_cache_size: usize,
72    /// Memory bandwidth (GB/s)
73    pub memory_bandwidth: f64,
74    /// NUMA nodes available
75    pub num_numa_nodes: usize,
76    /// GPU availability
77    pub has_gpu: bool,
78    /// SIMD width (e.g., 256 for AVX2, 512 for AVX-512)
79    pub simd_width: usize,
80}
81/// Parallelization analysis results
82#[derive(Debug, Clone)]
83pub struct ParallelizationAnalysis {
84    /// Parallel tasks generated
85    pub tasks: Vec<ParallelTask>,
86    /// Total number of layers
87    pub num_layers: usize,
88    /// Parallelization efficiency (0.0 to 1.0)
89    pub efficiency: f64,
90    /// Maximum parallelism achievable
91    pub max_parallelism: usize,
92    /// Critical path length
93    pub critical_path_length: usize,
94    /// Resource utilization predictions
95    pub resource_utilization: ResourceUtilization,
96    /// Optimization recommendations
97    pub recommendations: Vec<OptimizationRecommendation>,
98}
99/// Node capacity information for distributed task scheduling
100#[derive(Debug, Clone)]
101pub struct NodeCapacity {
102    /// Number of CPU cores available
103    pub cpu_cores: usize,
104    /// Available memory in GB
105    pub memory_gb: f64,
106    /// GPU availability
107    pub gpu_available: bool,
108    /// Network bandwidth in Gbps
109    pub network_bandwidth_gbps: f64,
110    /// Relative performance score (normalized)
111    pub relative_performance: f64,
112}
113/// Task completion statistics
114#[derive(Debug, Clone, Default)]
115pub struct TaskCompletionStats {
116    /// Total tasks completed
117    pub total_tasks: usize,
118    /// Average task duration
119    pub average_duration: Duration,
120    /// Task success rate
121    pub success_rate: f64,
122    /// Load balancing effectiveness
123    pub load_balance_effectiveness: f64,
124}
125/// Load balancer for parallel task execution
126pub struct LoadBalancer {
127    /// Current thread loads
128    thread_loads: Vec<f64>,
129    /// Task queue per thread
130    task_queues: Vec<VecDeque<ParallelTask>>,
131    /// Work stealing statistics
132    work_stealing_stats: WorkStealingStats,
133}
134impl LoadBalancer {
135    /// Create a new load balancer
136    #[must_use]
137    pub fn new(num_threads: usize) -> Self {
138        Self {
139            thread_loads: vec![0.0; num_threads],
140            task_queues: vec![VecDeque::new(); num_threads],
141            work_stealing_stats: WorkStealingStats::default(),
142        }
143    }
144    /// Balance load across threads
145    pub fn balance_load(&mut self, tasks: Vec<ParallelTask>) -> Vec<Vec<ParallelTask>> {
146        let mut balanced_tasks = vec![Vec::new(); self.thread_loads.len()];
147        for (i, task) in tasks.into_iter().enumerate() {
148            let thread_index = i % self.thread_loads.len();
149            balanced_tasks[thread_index].push(task);
150        }
151        balanced_tasks
152    }
153}
154/// Resource utilization predictions
155#[derive(Debug, Clone)]
156pub struct ResourceUtilization {
157    /// Estimated CPU utilization per thread
158    pub cpu_utilization: Vec<f64>,
159    /// Estimated memory usage per thread
160    pub memory_usage: Vec<usize>,
161    /// Load balancing score (0.0 to 1.0)
162    pub load_balance_score: f64,
163    /// Communication overhead estimate
164    pub communication_overhead: f64,
165}
166/// Work stealing statistics
167#[derive(Debug, Clone, Default)]
168pub struct WorkStealingStats {
169    /// Total steal attempts
170    pub steal_attempts: usize,
171    /// Successful steals
172    pub successful_steals: usize,
173    /// Failed steals
174    pub failed_steals: usize,
175    /// Average steal latency
176    pub average_steal_latency: Duration,
177}
178/// Parallelization results for a single circuit
179#[derive(Debug, Clone)]
180pub struct CircuitParallelResult {
181    /// Circuit size (number of gates)
182    pub circuit_size: usize,
183    /// Number of qubits
184    pub num_qubits: usize,
185    /// Time to analyze parallelization
186    pub analysis_time: Duration,
187    /// Parallelization efficiency
188    pub efficiency: f64,
189    /// Maximum parallelism achieved
190    pub max_parallelism: usize,
191    /// Number of parallel tasks generated
192    pub num_tasks: usize,
193}
194/// Task priority levels
195#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)]
196pub enum TaskPriority {
197    /// Low priority task
198    Low = 1,
199    /// Normal priority task
200    Normal = 2,
201    /// High priority task
202    High = 3,
203    /// Critical priority task
204    Critical = 4,
205}
206/// Gate node in the dependency graph
207#[derive(Debug, Clone)]
208pub struct GateNode {
209    /// Gate index in original circuit
210    pub gate_index: usize,
211    /// Gate operation
212    pub gate: Arc<dyn GateOp + Send + Sync>,
213    /// Qubits this gate operates on
214    pub qubits: HashSet<QubitId>,
215    /// Layer index in topological ordering
216    pub layer: usize,
217    /// Estimated execution cost
218    pub cost: f64,
219}
220/// Load balancing configuration for parallel execution
221#[derive(Debug, Clone, Serialize, Deserialize)]
222pub struct LoadBalancingConfig {
223    /// Enable dynamic load balancing
224    pub enable_dynamic_balancing: bool,
225    /// Work stealing strategy
226    pub work_stealing_strategy: WorkStealingStrategy,
227    /// Load monitoring interval
228    pub monitoring_interval: Duration,
229    /// Rebalancing threshold
230    pub rebalancing_threshold: f64,
231}
232/// Circuit dependency graph for parallelization analysis
233#[derive(Debug, Clone)]
234pub struct DependencyGraph {
235    /// Gate nodes in the dependency graph
236    pub nodes: Vec<GateNode>,
237    /// Adjacency list representation
238    pub edges: HashMap<usize, Vec<usize>>,
239    /// Reverse adjacency list
240    pub reverse_edges: HashMap<usize, Vec<usize>>,
241    /// Topological layers
242    pub layers: Vec<Vec<usize>>,
243}
244/// Configuration for automatic parallelization
245#[derive(Debug, Clone, Serialize, Deserialize)]
246pub struct AutoParallelConfig {
247    /// Maximum number of parallel execution threads
248    pub max_threads: usize,
249    /// Minimum gate count to enable parallelization
250    pub min_gates_for_parallel: usize,
251    /// Parallelization strategy
252    pub strategy: ParallelizationStrategy,
253    /// Resource constraints
254    pub resource_constraints: ResourceConstraints,
255    /// Enable inter-layer parallelization
256    pub enable_inter_layer_parallel: bool,
257    /// Enable gate fusion optimization
258    pub enable_gate_fusion: bool,
259    /// `SciRS2` optimization level
260    pub scirs2_optimization_level: OptimizationLevel,
261    /// Load balancing configuration
262    pub load_balancing: LoadBalancingConfig,
263    /// Enable circuit analysis caching
264    pub enable_analysis_caching: bool,
265    /// Memory budget for parallel execution
266    pub memory_budget: usize,
267}
268/// Parallel execution task representing a group of independent gates
269#[derive(Debug, Clone)]
270pub struct ParallelTask {
271    /// Unique task identifier
272    pub id: Uuid,
273    /// Gates to execute in this task
274    pub gates: Vec<Arc<dyn GateOp + Send + Sync>>,
275    /// Qubits involved in this task
276    pub qubits: HashSet<QubitId>,
277    /// Estimated execution cost
278    pub cost: f64,
279    /// Memory requirement estimate
280    pub memory_requirement: usize,
281    /// Dependencies (task IDs that must complete before this task)
282    pub dependencies: HashSet<Uuid>,
283    /// Priority level
284    pub priority: TaskPriority,
285}
286/// Complexity levels for recommendations
287#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)]
288pub enum RecommendationComplexity {
289    /// Low complexity, easy to implement
290    Low,
291    /// Medium complexity
292    Medium,
293    /// High complexity, significant changes required
294    High,
295}
296/// Performance statistics for parallel execution
297#[derive(Debug, Clone, Default)]
298pub struct ParallelPerformanceStats {
299    /// Total circuits processed
300    pub circuits_processed: usize,
301    /// Total execution time
302    pub total_execution_time: Duration,
303    /// Average parallelization efficiency
304    pub average_efficiency: f64,
305    /// Cache hit rate
306    pub cache_hit_rate: f64,
307    /// Task completion statistics
308    pub task_stats: TaskCompletionStats,
309    /// Resource utilization history
310    pub resource_history: Vec<ResourceSnapshot>,
311}
312/// Optimization recommendations for better parallelization
313#[derive(Debug, Clone)]
314pub struct OptimizationRecommendation {
315    /// Recommendation type
316    pub recommendation_type: RecommendationType,
317    /// Description of the recommendation
318    pub description: String,
319    /// Expected improvement (0.0 to 1.0)
320    pub expected_improvement: f64,
321    /// Implementation complexity
322    pub complexity: RecommendationComplexity,
323}
324/// Work stealing strategies for load balancing
325#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
326pub enum WorkStealingStrategy {
327    /// Random work stealing
328    Random,
329    /// Cost-aware work stealing
330    CostAware,
331    /// Locality-aware work stealing
332    LocalityAware,
333    /// Adaptive strategy selection
334    Adaptive,
335}
336/// `SciRS2` optimization levels
337#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
338pub enum OptimizationLevel {
339    /// No optimization
340    None,
341    /// Basic optimizations
342    Basic,
343    /// Advanced optimizations
344    Advanced,
345    /// Aggressive optimizations
346    Aggressive,
347    /// Custom optimization profile
348    Custom,
349}
350/// Resource constraints for parallel execution
351#[derive(Debug, Clone, Serialize, Deserialize)]
352pub struct ResourceConstraints {
353    /// Maximum memory per thread (bytes)
354    pub max_memory_per_thread: usize,
355    /// Maximum CPU utilization (0.0 to 1.0)
356    pub max_cpu_utilization: f64,
357    /// Maximum gate operations per thread
358    pub max_gates_per_thread: usize,
359    /// Preferred NUMA node
360    pub preferred_numa_node: Option<usize>,
361}
362/// Resource utilization snapshot
363#[derive(Debug, Clone)]
364pub struct ResourceSnapshot {
365    /// Timestamp
366    pub timestamp: Instant,
367    /// CPU utilization per core
368    pub cpu_utilization: Vec<f64>,
369    /// Memory usage
370    pub memory_usage: usize,
371    /// Active tasks
372    pub active_tasks: usize,
373}
374/// Results from automatic parallelization benchmark
375#[derive(Debug, Clone)]
376pub struct AutoParallelBenchmarkResults {
377    /// Total benchmark time
378    pub total_time: Duration,
379    /// Results for individual circuits
380    pub circuit_results: Vec<CircuitParallelResult>,
381    /// Average parallelization efficiency
382    pub average_efficiency: f64,
383    /// Average maximum parallelism
384    pub average_parallelism: usize,
385}
386/// Parallelization strategies for circuit execution
387#[derive(Debug, Clone, Copy, PartialEq, Eq, Serialize, Deserialize)]
388pub enum ParallelizationStrategy {
389    /// Analyze gate dependencies and parallelize independent operations
390    DependencyAnalysis,
391    /// Layer-based parallelization with depth analysis
392    LayerBased,
393    /// Qubit partitioning for independent subsystems
394    QubitPartitioning,
395    /// Hybrid approach combining multiple strategies
396    Hybrid,
397    /// Machine learning guided parallelization
398    MLGuided,
399    /// Hardware-aware parallelization
400    HardwareAware,
401}
402/// ML-predicted parallelization strategies
403#[derive(Debug, Clone, Copy, PartialEq, Eq)]
404pub enum MLPredictedStrategy {
405    /// High parallelism - aggressive parallel execution
406    HighParallelism,
407    /// Balanced parallelism - mixed approach
408    BalancedParallelism,
409    /// Conservative parallelism - careful dependency management
410    ConservativeParallelism,
411    /// Layer-optimized execution
412    LayerOptimized,
413}
quantrs2_sim/automatic_parallelization/types.rs

quantrs2_sim/automatic_parallelization/
types.rs
