Expand description
Enhanced Gate Translation Algorithms for Device-Specific Gate Sets
This module provides sophisticated translation algorithms that can convert quantum circuits between different gate sets while optimizing for hardware constraints, fidelity requirements, and performance objectives.
Structs§
- Circuit
Info - Circuit information
- Gate
Pattern - Pattern for matching source gates
- Gate
SetSpecification - Gate set specification
- Gate
Translation Metadata - Metadata for individual gate translation
- Gate
Translator - Gate translation engine
- Parameter
Constraints - Parameter constraints for gates
- Rule
Metadata - Metadata for translation rules
- Target
Gate - Target gate in translation
- Translated
Circuit - Translated circuit representation
- Translated
Gate - Individual translated gate
- Translation
Cache - Cache for translated circuits
- Translation
Cache Entry - Cache entry for translations
- Translation
Cache Stats - Cache statistics
- Translation
Cost - Cost model for translations
- Translation
Metadata - Translation metadata
- Translation
Performance Monitor - Performance monitoring for translations
- Translation
Performance Stats - Translation performance statistics
- Translation
Quality Metrics - Translation quality metrics
- Translation
Rule - Translation rule between gate sets
- Translation
Rule Database - Database of translation rules
- Translation
Summary - Translation summary
- Translation
Verification Engine - Verification engine for translations
- Verification
Result - Verification result
Enums§
- Gate
Type - Generic gate type for translation
- Parameter
Expression - Parameter expression for target gates
- Parameter
Pattern - Parameter pattern for matching
- Qubit
Pattern - Qubit connectivity pattern
- Translation
Condition - Conditions for applying translation rules
- Translation
Strategy - Translation strategy
- Universal
Gate Set - Universal gate set definitions
Traits§
- Verification
Strategy - Verification strategy trait