qrc_opensource_rs/common/
common.rs

1/* The AGPL version 3 License (AGPLv3)
2* 
3* Copyright (c) 2021 Digital Freedom Defence Inc.
4* This file is part of the QSC Cryptographic library
5* 
6* This program is free software : you can redistribute it and / or modify
7* it under the terms of the GNU Affero General Public License as published by
8* the Free Software Foundation, either version 3 of the License, or
9* (at your option) any later version.
10* 
11* This program is distributed in the hope that it will be useful,
12* but WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14* See the GNU Affero General Public License for more details.
15* 
16* You should have received a copy of the GNU Affero General Public License
17* along with this program. If not, see <http://www.gnu.org/licenses/>.
18*
19*
20*
21* Copyright (c) Original-2021 John G. Underhill <john.underhill@mailfence.com>
22* Copyright (c) 2022-Present QRC Eurosmart SA <opensource-support@qrcrypto.ch>
23*
24* The following code is a derivative work of the code from the QSC Cryptographic library in C, 
25* which is licensed AGPLv3. This code therefore is also licensed under the terms of 
26* the GNU Affero General Public License, version 3. The AGPL version 3 License (AGPLv3). */
27
28pub const QRC_MAX_MEMORY_CLEAR: bool = !cfg!(feature = "MIN_MEMORY_CLEAR");
29
30/*
31\def QRC_SYSTEM_OS_XXX
32* \brief The identified operating system
33*/
34pub const QRC_SYSTEM_OS_WINDOWS: bool = cfg!(target_os = "windows");
35    pub const QRC_SYSTEM_ISWIN64: bool = cfg!(target_pointer_width = "64") && QRC_SYSTEM_OS_WINDOWS;
36    pub const QRC_SYSTEM_ISWIN32: bool = cfg!(target_pointer_width = "32") && QRC_SYSTEM_OS_WINDOWS;
37
38pub const QRC_SYSTEM_OS_ANDROID: bool = cfg!(target_os = "android");
39
40pub const QRC_SYSTEM_OS_APPLE: bool = cfg!(target_vendor = "apple");
41    pub const TARGET_OS_IPHONE: bool = cfg!(target_os = "ios") && QRC_SYSTEM_OS_APPLE;
42    pub const TARGET_IPHONE_SIMULATOR: bool = !TARGET_OS_IPHONE; //Treat simulator as real
43
44    pub const QRC_SYSTEM_ISIPHONE: bool = TARGET_OS_IPHONE && !TARGET_IPHONE_SIMULATOR;
45    pub const QRC_SYSTEM_ISIPHONESIM: bool = TARGET_OS_IPHONE && TARGET_IPHONE_SIMULATOR;
46
47    pub const QRC_SYSTEM_ISOSX: bool = cfg!(target_os = "macos") && QRC_SYSTEM_OS_APPLE;
48
49pub const QRC_SYSTEM_OS_BSD: bool = cfg!(any(target_os = "freebsd", target_os = "openbsd", target_os = "netbsd", target_os = "dragonfly")) || QRC_SYSTEM_OS_APPLE;
50
51pub const QRC_SYSTEM_OS_LINUX: bool = cfg!(target_os = "linux") && !QRC_SYSTEM_OS_ANDROID && !QRC_SYSTEM_OS_BSD;
52
53pub const QRC_SYSTEM_OS_UNIX: bool = cfg!(target_family = "unix") && !QRC_SYSTEM_OS_ANDROID && !QRC_SYSTEM_OS_BSD && !QRC_SYSTEM_OS_LINUX;
54    //pub const QRC_SYSTEM_OS_HPUX: bool = cfg!(target_os = "hpux") && QRC_SYSTEM_OS_UNIX;
55    pub const QRC_SYSTEM_OS_SUNUX: bool = cfg!(target_os = "solaris") && QRC_SYSTEM_OS_UNIX;
56
57pub const QRC_SYSTEM_OS_POSIX: bool = QRC_SYSTEM_OS_ANDROID || QRC_SYSTEM_OS_APPLE || QRC_SYSTEM_OS_BSD || QRC_SYSTEM_OS_LINUX || QRC_SYSTEM_OS_UNIX;
58
59pub const QRC_DEBUG_MODE: bool = cfg!(debug_assertions);
60
61
62/*
63\def QRC_SYSTEM_ARCH_XXX
64* \brief The CPU architecture
65*/
66pub const QRC_SYSTEM_ARCH_IX86: bool = cfg!(any(target_arch = "x86", target_arch = "x86_64"));
67    pub const QRC_SYSTEM_ARCH_IX86_64: bool = cfg!(target_arch = "x86_64") && QRC_SYSTEM_ARCH_IX86;
68    pub const QRC_SYSTEM_ARCH_AMD64: bool = cfg!(target_arch = "x86_64") && QRC_SYSTEM_ARCH_IX86;
69    pub const QRC_SYSTEM_ARCH_IX86_32: bool = cfg!(target_arch = "x86") && QRC_SYSTEM_ARCH_IX86;
70
71pub const QRC_SYSTEM_ARCH_ARM: bool = cfg!(any(target_arch = "arm", target_arch = "aarch64"));
72    pub const QRC_SYSTEM_ARCH_ARMV7VE: bool = cfg!(target_feature = "v7") && QRC_SYSTEM_ARCH_ARM;
73    //pub const QRC_SYSTEM_ARCH_ARMFP: bool = cfg!(target_feature = "fp") && QRC_SYSTEM_ARCH_ARM;
74    pub const QRC_SYSTEM_ARCH_ARM64: bool = cfg!(target_arch = "aarch64") && QRC_SYSTEM_ARCH_ARM;
75
76//pub const QRC_SYSTEM_ARCH_IA64: bool = cfg!(target_arch = "ia64");
77
78pub const QRC_SYSTEM_ARCH_PPC: bool = cfg!(any(target_arch = "powerpc", target_arch = "powerpc64"));
79
80pub const QRC_SYSTEM_ARCH_SPARC: bool = cfg!(target_arch = "sparc");
81    pub const QRC_SYSTEM_ARCH_SPARC64: bool = cfg!(target_arch = "sparc64") && QRC_SYSTEM_ARCH_SPARC;
82
83
84/*
85\def QRC_SYSTEM_IS_LITTLE_ENDIAN
86* \brief The system is little endian
87*/
88pub const QRC_SYSTEM_IS_LITTLE_ENDIAN: bool = cfg!(target_endian = "little");
89pub const QRC_SYSTEM_IS_BIG_ENDIAN: bool = cfg!(target_endian = "big");
90
91
92/*
93\def QRC_SYSTEM_MAX_PATH
94* \brief The maximum path length
95*/
96pub const QRC_SYSTEM_MAX_PATH: usize = 260;
97
98/*
99\def QRC_SYSTEM_SECMEMALLOC_DEFAULT
100* \brief The secure memory default buffer allocation
101*/
102pub const QRC_SYSTEM_SECMEMALLOC_DEFAULT: usize = 4096;
103
104/*
105\def QRC_SYSTEM_SECMEMALLOC_MIN
106* \brief The minimum secure memory allocation
107*/
108pub const QRC_SYSTEM_SECMEMALLOC_MIN: usize = 16;
109
110/*
111\def QRC_SYSTEM_SECMEMALLOC_MAX
112* \brief The maximum secure memory allocation
113*/
114pub const QRC_SYSTEM_SECMEMALLOC_MAX: usize = 128;
115
116/*
117\def QRC_SYSTEM_SECMEMALLOC_MAXKB
118* \brief The secure memory maximum allocation in kilobytes
119*/
120pub const QRC_SYSTEM_SECMEMALLOC_MAXKB: usize = 512;
121
122/*
123* AVX512 Capabilities Check
124* https://software.intel.com/en-us/intel-cplusplus-compiler-16.0-user-and-reference-guide
125* https://software.intel.com/en-us/articles/compiling-for-the-intel-xeon-phi-processor-and-the-intel-avx-512-isa
126* https://colfaxresearch.com/knl-avx512/
127*
128* #include <immintrin.h>
129* supported is 1: ex. __AVX512CD__ 1
130* F		__AVX512F__					Foundation
131* CD	__AVX512CD__				Conflict Detection Instructions(CDI)
132* ER	__AVX512ER__				Exponential and Reciprocal Instructions(ERI)
133* PF	__AVX512PF__				Pre-fetch Instructions(PFI)
134* DQ	__AVX512DQ__				Double-word and Quadword Instructions(DQ)
135* BW	__AVX512BW__				Byte and Word Instructions(BW)
136* VL	__AVX512VL__				Vector Length Extensions(VL)
137* IFMA	__AVX512IFMA__				Integer Fused Multiply Add(IFMA)
138* VBMI	__AVX512VBMI__				Vector Byte Manipulation Instructions(VBMI)
139* VNNIW	__AVX5124VNNIW__			Vector instructions for deep learning enhanced word variable precision
140* FMAPS	__AVX5124FMAPS__			Vector instructions for deep learning floating - point single precision
141* VPOPCNT	__AVX512VPOPCNTDQ__		?
142*
143* Note: AVX512 is currently untested, this flag enables support on a compliant system
144*/
145/* Enable this define to support AVX512 on a compatible system */
146
147/*
148\def QRC_SYSTEM_HAS_SSE2
149* \brief The system supports SSE2 instructions
150*/
151pub const QRC_SYSTEM_HAS_SSE2: bool = cfg!(target_feature = "sse2");
152
153/*
154\def QRC_SYSTEM_HAS_SSE3
155* \brief The system supports SSE3 instructions
156*/
157pub const QRC_SYSTEM_HAS_SSE3: bool = cfg!(target_feature = "sse3");
158
159/*
160\def QRC_SYSTEM_HAS_SSSE3
161* \brief The system supports SSSE3 instructions
162*/
163pub const QRC_SYSTEM_HAS_SSSE3: bool = cfg!(target_feature = "ssse3");
164
165/*
166\def QRC_SYSTEM_HAS_SSE41
167* \brief The system supports SSE41 instructions
168*/
169pub const QRC_SYSTEM_HAS_SSE41: bool = cfg!(target_feature = "sse4.1");
170
171/*
172\def QRC_SYSTEM_HAS_SSE42
173* \brief The system supports SSE42 instructions
174*/
175pub const QRC_SYSTEM_HAS_SSE42: bool = cfg!(target_feature = "sse4.2");
176
177/*
178\def QRC_SYSTEM_HAS_AVX
179* \brief The system supports AVX instructions
180*/
181pub const QRC_SYSTEM_HAS_AVX: bool = cfg!(target_feature = "avx");
182
183/*
184\def QRC_SYSTEM_HAS_AVX2
185* \brief The system supports AVX2 instructions
186*/
187pub const QRC_SYSTEM_HAS_AVX2: bool = cfg!(target_feature = "avx2");
188
189/*
190\def QRC_SYSTEM_HAS_AVX512
191* \brief The system supports AVX512 instructions
192*/
193pub const QRC_SYSTEM_HAS_AVX512: bool = cfg!(target_feature = "avx512f");
194
195//pub const QRC_SYSTEM_HAS_XOP: bool = cfg!(target_feature = "xop");
196
197/*
198\def QRC_SYSTEM_AVX_INTRINSICS
199* \brief The system supports AVX instructions
200*/
201pub const QRC_SYSTEM_AVX_INTRINSICS: bool = QRC_SYSTEM_HAS_AVX || QRC_SYSTEM_HAS_AVX2 || QRC_SYSTEM_HAS_AVX512;
202
203/*
204\def QRC_SIMD_ALIGN
205* \brief Align an array by SIMD instruction width
206*/
207pub const QRC_SIMD_ALIGNMENT: usize = if QRC_SYSTEM_HAS_AVX512 {
208    64
209} else if QRC_SYSTEM_HAS_AVX2 {
210    32
211} else if QRC_SYSTEM_HAS_AVX {
212    16
213} else {
214    8
215};
216
217/*
218* \def QRC_RDRAND_COMPATIBLE
219* \brief The system has an RDRAND compatible CPU
220*/
221pub const QRC_RDRAND_COMPATIBLE: bool = QRC_SYSTEM_AVX_INTRINSICS;
222
223/*
224\def QRC_STATUS_SUCCESS
225* Function return value indicates successful operation
226*/
227pub const QRC_STATUS_SUCCESS: i32 = 0;
228
229/*
230\def QRC_STATUS_FAILURE
231* Function return value indicates failed operation
232*/
233pub const QRC_STATUS_FAILURE: i32 = -1;
234
235
236/* User Modifiable Values
237* Modifiable values that determine which parameter sets and options get compiled.
238* These values can be tuned by the user to enable/disable features for a specific environment, or hardware configuration.
239* This list also includes the asymmetric cipher and signature scheme parameter set options.
240*/
241
242/*
243\def QRC_SYSTEM_AESNI_ENABLED
244* Enable the use of intrinsics and the AES-NI implementation.
245* Just for testing, add the QRC_SYSTEM_AESNI_ENABLED preprocessor definition and enable SIMD and AES-NI.
246*/
247
248pub const QRC_SYSTEM_AESNI_ENABLED: bool = QRC_SYSTEM_AVX_INTRINSICS;
249
250/*
251* \def QRC_KECCAK_UNROLLED_PERMUTATION
252* \brief Define to use the UNROLLED form of the Keccak permutation function
253* if undefined, functions use the compact form of the Keccak permutation
254*/
255//pub const QRC_KECCAK_UNROLLED_PERMUTATION: bool = cfg!(feature = "KECCAK_UNROLLED_PERMUTATION");
256
257
258
259#[macro_export]
260macro_rules! assert_unique_feature {
261    () => {};
262    ($first:tt $(,$rest:tt)*) => {
263        $(
264            #[cfg(all(feature = $first, feature = $rest))]
265            compile_error!(concat!("features \"", $first, "\" and \"", $rest, "\" cannot be used together"));
266        )*
267        assert_unique_feature!($($rest),*);
268    }
269}
270
271/*** Asymmetric Ciphers ***/
272
273/*** ECDH ***/
274
275/*
276\def QRC_ECDH_S1EC25519
277* Implement the ECDH S1EC25519 parameter set
278*/
279pub const QRC_ECDH_S1EC25519: bool = cfg!(any(feature = "ECDH_S1EC25519", not(any())));
280
281/*** Kyber ***/
282assert_unique_feature!("KYBER_S3Q3329N256K3", "KYBER_S5Q3329N256K4", "KYBER_S6Q3329N256K5");
283/*
284\def QRC_KYBER_S3Q3329N256K3
285* Implement the Kyber S3Q3329N256K3 parameter set
286*/
287pub const QRC_KYBER_S3Q3329N256K3: bool = cfg!(feature = "KYBER_S3Q3329N256K3");
288
289/*
290\def QRC_KYBER_S5Q3329N256K4
291* Implement the Kyber S5Q3329N256K4 parameter set
292*/
293pub const QRC_KYBER_S5Q3329N256K4: bool = cfg!(any(feature = "KYBER_S5Q3329N256K4", not(any(feature = "KYBER_S3Q3329N256K3", feature = "KYBER_S6Q3329N256K5"))));
294
295/*
296\def QRC_KYBER_S6Q3329N256K5
297* Implement the Kyber S6Q3329N256K5 parameter set.
298* /warning Experimental, not an official parameter.
299*/
300pub const QRC_KYBER_S6Q3329N256K5: bool = cfg!(feature = "KYBER_S6Q3329N256K5");
301
302/*** McEliece ***/
303assert_unique_feature!("MCELIECE_S3N4608T96", "MCELIECE_S5N6688T128", "MCELIECE_S5N6960T119", "MCELIECE_S5N8192T128");
304/*
305\def QRC_MCELIECE_S3N4608T96
306* Implement the McEliece S3-N4608T96 parameter set
307*/
308pub const QRC_MCELIECE_S3N4608T96: bool = cfg!(feature = "MCELIECE_S3N4608T96");
309
310/*
311\def QRC_MCELIECE_S5N6688T128
312* Implement the McEliece S5-N6688T128 parameter set
313*/
314pub const QRC_MCELIECE_S5N6688T128: bool = cfg!(any(feature = "MCELIECE_S5N6688T128", not(any(feature = "MCELIECE_S3N4608T96", feature = "MCELIECE_S5N6960T119", feature = "MCELIECE_S5N8192T128"))));
315
316/*
317\def QRC_MCELIECE_S5N6960T119
318* Implement the McEliece S5-N6960T119 parameter set
319*/
320pub const QRC_MCELIECE_S5N6960T119: bool = cfg!(feature = "MCELIECE_S5N6960T119");
321
322/*
323\def QRC_MCELIECE_S5N8192T128
324* Implement the McEliece S5-N8192T128 parameter set
325*/
326pub const QRC_MCELIECE_S5N8192T128: bool = cfg!(feature = "MCELIECE_S5N8192T128");
327
328/*** Signature Schemes ***/
329
330/*** Dilithium ***/
331assert_unique_feature!("DILITHIUM_S2N256Q8380417K4", "DILITHIUM_S3N256Q8380417K6", "DILITHIUM_S5N256Q8380417K8");
332/*
333\def QRC_DILITHIUM_S2N256Q8380417K4
334* Implement the Dilithium S2N256Q8380417 parameter set
335*/
336pub const QRC_DILITHIUM_S2N256Q8380417K4: bool = cfg!(feature = "DILITHIUM_S2N256Q8380417K4");
337
338/*
339\def QRC_DILITHIUM_S3N256Q8380417K6
340* Implement the Dilithium S3N256Q83804 parameter set
341*/
342pub const QRC_DILITHIUM_S3N256Q8380417K6: bool = cfg!(any(feature = "DILITHIUM_S3N256Q8380417K6", not(any(feature = "DILITHIUM_S2N256Q8380417K4", feature = "DILITHIUM_S5N256Q8380417K8"))));
343
344/*
345\def QRC_DILITHIUM_S5N256Q8380417K8
346* Implement the Dilithium S5N256Q8380417 parameter set
347*/
348pub const QRC_DILITHIUM_S5N256Q8380417K8: bool = cfg!(feature = "DILITHIUM_S5N256Q8380417K8");
349
350/*** ECDSA ***/
351
352/*
353\def QRC_ECDSA_S1EC25519
354* Implement the ECDSA S1EC25519 parameter set
355*/
356pub const QRC_ECDSA_S1EC25519: bool = cfg!(any(feature = "ECDSA_S1EC25519", not(any())));
357
358/*** Falcon ***/
359assert_unique_feature!("FALCON_S3SHAKE256F512", "FALCON_S5SHAKE256F1024");
360/*
361\def QRC_FALCON_S3SHAKE256F512
362* Implement the Falcon S3SHAKE256F512 parameter set
363*/
364pub const QRC_FALCON_S3SHAKE256F512: bool = cfg!(feature = "FALCON_S3SHAKE256F512");
365
366/*
367\def QRC_FALCON_S5SHAKE256F1024
368* Implement the Falcon S5SHAKE256F1024 parameter set
369*/
370pub const QRC_FALCON_S5SHAKE256F1024: bool = cfg!(any(feature = "FALCON_S5SHAKE256F1024", not(any(feature = "FALCON_S3SHAKE256F512"))));
371
372/*** SphincsPlus ***/
373assert_unique_feature!("SPHINCSPLUS_S3S192SHAKERS", "SPHINCSPLUS_S3S192SHAKERF", "SPHINCSPLUS_S5S256SHAKERS", "SPHINCSPLUS_S5S256SHAKERF");
374/*
375\def QRC_SPHINCSPLUS_S3S192SHAKERS
376* Implement the SphincsPlus S3S192SHAKERS robust small parameter set
377*/
378pub const QRC_SPHINCSPLUS_S3S192SHAKERS: bool = cfg!(feature = "SPHINCSPLUS_S3S192SHAKERS");
379
380/*
381\def QRC_SPHINCSPLUS_S3S192SHAKERF
382* Implement the SphincsPlus S3S192SHAKERF robust fast parameter set
383*/
384pub const QRC_SPHINCSPLUS_S3S192SHAKERF: bool = cfg!(feature = "SPHINCSPLUS_S3S192SHAKERF");
385
386/*
387\def QRC_SPHINCSPLUS_S5S256SHAKERS
388* Implement the SphincsPlus S5S256SHAKERS robust small parameter set
389*/
390pub const QRC_SPHINCSPLUS_S5S256SHAKERS: bool = cfg!(feature = "SPHINCSPLUS_S5S256SHAKERS");
391
392/*
393\def QRC_SPHINCSPLUS_S5S256SHAKERF
394* Implement the SphincsPlus S5S256SHAKERF robust fast parameter set
395*/
396pub const QRC_SPHINCSPLUS_S5S256SHAKERF: bool = cfg!(any(feature = "SPHINCSPLUS_S5S256SHAKERF", not(any(feature = "SPHINCSPLUS_S3S192SHAKERS", feature = "SPHINCSPLUS_S3S192SHAKERF", feature = "SPHINCSPLUS_S5S256SHAKERS"))));
qrc_opensource_rs/common/common.rs

qrc_opensource_rs/common/
common.rs
