q1tsim_logic_gates/
lib.rs

1pub mod q1tlogic {
2    extern crate q1tsim;
3    use q1tsim::{circuit, gates};
4
5    pub fn create_and(
6        circuit: &mut circuit::Circuit,
7        operand_qbits: Vec<usize>,
8        result_qbit: usize,
9    ) -> &circuit::Circuit {
10        let mut target_qbits = operand_qbits.clone();
11        target_qbits.push(result_qbit);
12
13        circuit
14            .add_gate(gates::CCX::new(), target_qbits.as_slice())
15            .unwrap();
16
17        circuit
18    }
19
20    pub fn create_or(
21        circuit: &mut circuit::Circuit,
22        operand_qbits: Vec<usize>,
23        result_qbit: usize,
24    ) -> &circuit::Circuit {
25        let mut target_qbits = operand_qbits.clone();
26        target_qbits.push(result_qbit);
27
28        circuit.cx(target_qbits[0], result_qbit).unwrap();
29        circuit.cx(target_qbits[1], result_qbit).unwrap();
30        circuit
31            .add_gate(gates::CCX::new(), target_qbits.as_slice())
32            .unwrap();
33
34        circuit
35    }
36
37    pub fn create_xor(
38        circuit: &mut circuit::Circuit,
39        operand_qbits: Vec<usize>,
40    ) -> &circuit::Circuit {
41        circuit.cx(operand_qbits[0], operand_qbits[1]).unwrap();
42        circuit.x(operand_qbits[1]).unwrap();
43
44        circuit
45    }
46}
47
48#[cfg(test)]
49mod tests {
50    extern crate q1tsim;
51    use crate::q1tlogic;
52    use q1tsim::circuit;
53
54    #[test]
55    fn test_create_and() {
56        let mut circuit = circuit::Circuit::new(3, 3);
57
58        circuit.h(0).unwrap();
59        circuit.h(1).unwrap();
60
61        q1tlogic::create_and(&mut circuit, vec![0, 1], 2);
62
63        circuit.measure_all(&[0, 1, 2]).unwrap();
64        circuit.execute(8192).unwrap();
65
66        let histo = circuit.histogram_string().unwrap();
67
68        let mut results: Vec<_> = histo.keys().collect();
69        results.sort();
70
71        assert_eq!(vec!["000", "001", "010", "111"], results);
72    }
73    #[test]
74    fn test_create_or() {
75        let mut circuit = circuit::Circuit::new(3, 3);
76
77        circuit.h(0).unwrap();
78        circuit.h(1).unwrap();
79
80        q1tlogic::create_or(&mut circuit, vec![0, 1], 2);
81
82        circuit.measure_all(&[0, 1, 2]).unwrap();
83        circuit.execute(8192).unwrap();
84
85        let histo = circuit.histogram_string().unwrap();
86
87        let mut results: Vec<_> = histo.keys().collect();
88        results.sort();
89
90        assert_eq!(vec!["000", "101", "110", "111"], results);
91    }
92
93    #[test]
94    fn test_create_xor() {
95        let mut circuit = circuit::Circuit::new(2, 2);
96        circuit.h(0).unwrap();
97        q1tlogic::create_xor(&mut circuit, vec![0, 1]);
98
99        circuit.measure_all(&[0, 1]).unwrap();
100        circuit.execute(8192).unwrap();
101
102        let histo = circuit.histogram_string().unwrap();
103
104        let mut results: Vec<_> = histo.keys().collect();
105        results.sort();
106
107        assert_eq!(vec!["01", "10"], results);
108    }
109}
q1tsim_logic_gates/lib.rs

q1tsim_logic_gates/
lib.rs
