pub struct Icm { /* fields omitted */ }
Expand description
ICM Peripheral
Encapsulates the PAC which acts as a token and provides an interface to the ICM hardware
Implementations
Create the interface for the ICM peripheral
Don’t forget to enable the APB
bus for ICM
AHB
bus is on by default at reset
Clock::v1
mclk.apbcmask.modify(|_, w| w.icm_().set_bit());
Clock::v2
tokens.apbs.icm.enable();
Get enabled status of the ICM peripheral
Reset the ICM controller
Does not seem to clear DSCR, HASH addr
The only way to clear the URAD
and URAT
fields
is by resetting the ICM controller
Enable region0
Creates an Region
which provides region specific
settings
Enable region1
Creates an Region
which provides region specific
settings
Enable region2
Creates an Region
which provides region specific
settings
Enable region3
Creates an Region
which provides region specific
settings
Helper for setting the HASH addr
Expects a raw pointer to the memory address of the beginning of the designated variable but expressed as a multiple of 128
Set the DSCR addr to a specific MainRegionDesc
HW expects a raw pointer to the memory address of the beginning of the
MainRegionDesc
but expressed as a multiple of 64
Set the user initial hash value
Set the user hashing algorithm
Activate user hash mode
Allows providing
- hash initial value
- Hash algorithm
Disables the ALGO
field in MainRegionDesc
Set initial hash value via Icm::set_user_initial_hash_value()
Set hash algorithm via Icm::set_user_algorithm()
Control dual input buffer
Enabling dual input buffering allow for better performance at the cost of higher bandwith requirements on the system bus
Automatic switch to Compare Digest
When activated, after the first Main List pass the ICM controller automatically switches to active monitoring.
CDWBN
and WBDIS
bits has no effects, to terminate the monitoring a
1
needs to be written to End of Monitoring (RCFG.EOM
)
Bus burden control
Set a delay between block transfers, calculated as
2.pow(busburden)
Maximum delay is 32768 cycles
Secondary List Branching Disable
- If set to false, allow secondary lists
- If set to true, secondary lists are forbidden,
NEXT
andRNEXT
is always considered 0.
End of Monitoring Disable
- If set to false, End of Monitoring is permitter
- If set to true, End of Monitoring is forbidden, the EOM bit in RCFG has no effect.
Write Back Disable
- If set to false, Write Back Operations are permitted
- If set to true, Write Back Operations are forbidden,
CDWBN
bit is internally set to 1 and cannot be modified by a linked list element. TheCDWBN
bit of theRCFG
structure member has no effect.
Set Undefined Register Access Detection interrupt enable
Disable Undefined Register Access Detection interrupt enable
Get Undefined Register Access Detection interrupt mask
Get Undefined Register Access Detection interrupt status
Get Undefined Register Access Trace
This field is only reset by swrst
When reading the interrupt (ISR) register, it is cleared
This might result in unexpected results for example when sequentially trying to determine which interrupt triggered.
This is an alternative, return all the data from the register
and parse later with the designated get_[name]_int
functions.
Trigger recalculation of memory monitor region specified by the bitmask: 0b0001 = region0 0b0010 = region1 0b0100 = region2 0b1000 = region3 … 0b1111 = all regions
Auto Trait Implementations
impl RefUnwindSafe for Icm
impl UnwindSafe for Icm
Blanket Implementations
Mutably borrows from an owned value. Read more
Casts the value.
Casts the value.
Casts the value.
OverflowingCasts the value.
Casts the value.
Casts the value.
Casts the value.
UnwrappedCasts the value.
Casts the value.
WrappingCasts the value.