py32f0/py32f040/usart1/
brr.rs

1///Register `BRR` reader
2pub struct R(crate::R<BRR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<BRR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<BRR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<BRR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `BRR` writer
17pub struct W(crate::W<BRR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<BRR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<BRR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<BRR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `DIV_Fraction` reader - desc DIV_Fraction
38pub type DIV_FRACTION_R = crate::FieldReader<u8, u8>;
39///Field `DIV_Fraction` writer - desc DIV_Fraction
40pub type DIV_FRACTION_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, BRR_SPEC, u8, u8, 4, O>;
41///Field `DIV_Mantissa` reader - desc DIV_Mantissa
42pub type DIV_MANTISSA_R = crate::FieldReader<u16, u16>;
43///Field `DIV_Mantissa` writer - desc DIV_Mantissa
44pub type DIV_MANTISSA_W<'a, const O: u8> =
45    crate::FieldWriterSafe<'a, u32, BRR_SPEC, u16, u16, 12, O>;
46impl R {
47    ///Bits 0:3 - desc DIV_Fraction
48    #[inline(always)]
49    pub fn div_fraction(&self) -> DIV_FRACTION_R {
50        DIV_FRACTION_R::new((self.bits & 0x0f) as u8)
51    }
52    ///Bits 4:15 - desc DIV_Mantissa
53    #[inline(always)]
54    pub fn div_mantissa(&self) -> DIV_MANTISSA_R {
55        DIV_MANTISSA_R::new(((self.bits >> 4) & 0x0fff) as u16)
56    }
57}
58impl W {
59    ///Bits 0:3 - desc DIV_Fraction
60    #[inline(always)]
61    #[must_use]
62    pub fn div_fraction(&mut self) -> DIV_FRACTION_W<0> {
63        DIV_FRACTION_W::new(self)
64    }
65    ///Bits 4:15 - desc DIV_Mantissa
66    #[inline(always)]
67    #[must_use]
68    pub fn div_mantissa(&mut self) -> DIV_MANTISSA_W<4> {
69        DIV_MANTISSA_W::new(self)
70    }
71    ///Writes raw bits to the register.
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78/**desc BRR
79
80This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
81
82For information about available fields see [brr](index.html) module*/
83pub struct BRR_SPEC;
84impl crate::RegisterSpec for BRR_SPEC {
85    type Ux = u32;
86}
87///`read()` method returns [brr::R](R) reader structure
88impl crate::Readable for BRR_SPEC {
89    type Reader = R;
90}
91///`write(|w| ..)` method takes [brr::W](W) writer structure
92impl crate::Writable for BRR_SPEC {
93    type Writer = W;
94    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
95    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
96}
97///`reset()` method sets BRR to value 0
98impl crate::Resettable for BRR_SPEC {
99    const RESET_VALUE: Self::Ux = 0;
100}
py32f0/py32f040/usart1/brr.rs

py32f0/py32f040/usart1/
brr.rs
