py32f0/py32f040/tim3/
ccmr2_output.rs

1///Register `CCMR2_OUTPUT` reader
2pub struct R(crate::R<CCMR2_OUTPUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCMR2_OUTPUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCMR2_OUTPUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCMR2_OUTPUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CCMR2_OUTPUT` writer
17pub struct W(crate::W<CCMR2_OUTPUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCMR2_OUTPUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCMR2_OUTPUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCMR2_OUTPUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CC3S` reader - desc CC3S
38pub type CC3S_R = crate::FieldReader<u8, CC3S_A>;
39/**desc CC3S
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u8)]
44pub enum CC3S_A {
45    ///0: CCx channel is configured as output
46    Output = 0,
47}
48impl From<CC3S_A> for u8 {
49    #[inline(always)]
50    fn from(variant: CC3S_A) -> Self {
51        variant as _
52    }
53}
54impl CC3S_R {
55    ///Get enumerated values variant
56    #[inline(always)]
57    pub fn variant(&self) -> Option<CC3S_A> {
58        match self.bits {
59            0 => Some(CC3S_A::Output),
60            _ => None,
61        }
62    }
63    ///Checks if the value of the field is `Output`
64    #[inline(always)]
65    pub fn is_output(&self) -> bool {
66        *self == CC3S_A::Output
67    }
68}
69///Field `CC3S` writer - desc CC3S
70pub type CC3S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, CC3S_A, 2, O>;
71impl<'a, const O: u8> CC3S_W<'a, O> {
72    ///CCx channel is configured as output
73    #[inline(always)]
74    pub fn output(self) -> &'a mut W {
75        self.variant(CC3S_A::Output)
76    }
77}
78///Field `OC3FE` reader - desc OC3FE
79pub type OC3FE_R = crate::BitReader<OC3FE_A>;
80/**desc OC3FE
81
82Value on reset: 0*/
83#[derive(Clone, Copy, Debug, PartialEq, Eq)]
84pub enum OC3FE_A {
85    ///0: Output compare 3 fast disabled
86    Disabled = 0,
87    ///1: Output compare 3 fast enabled
88    Enabled = 1,
89}
90impl From<OC3FE_A> for bool {
91    #[inline(always)]
92    fn from(variant: OC3FE_A) -> Self {
93        variant as u8 != 0
94    }
95}
96impl OC3FE_R {
97    ///Get enumerated values variant
98    #[inline(always)]
99    pub fn variant(&self) -> OC3FE_A {
100        match self.bits {
101            false => OC3FE_A::Disabled,
102            true => OC3FE_A::Enabled,
103        }
104    }
105    ///Checks if the value of the field is `Disabled`
106    #[inline(always)]
107    pub fn is_disabled(&self) -> bool {
108        *self == OC3FE_A::Disabled
109    }
110    ///Checks if the value of the field is `Enabled`
111    #[inline(always)]
112    pub fn is_enabled(&self) -> bool {
113        *self == OC3FE_A::Enabled
114    }
115}
116///Field `OC3FE` writer - desc OC3FE
117pub type OC3FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, OC3FE_A, O>;
118impl<'a, const O: u8> OC3FE_W<'a, O> {
119    ///Output compare 3 fast disabled
120    #[inline(always)]
121    pub fn disabled(self) -> &'a mut W {
122        self.variant(OC3FE_A::Disabled)
123    }
124    ///Output compare 3 fast enabled
125    #[inline(always)]
126    pub fn enabled(self) -> &'a mut W {
127        self.variant(OC3FE_A::Enabled)
128    }
129}
130///Field `OC3PE` reader - desc OC3PE
131pub type OC3PE_R = crate::BitReader<OC3PE_A>;
132/**desc OC3PE
133
134Value on reset: 0*/
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum OC3PE_A {
137    ///0: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
138    Disabled = 0,
139    ///1: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
140    Enabled = 1,
141}
142impl From<OC3PE_A> for bool {
143    #[inline(always)]
144    fn from(variant: OC3PE_A) -> Self {
145        variant as u8 != 0
146    }
147}
148impl OC3PE_R {
149    ///Get enumerated values variant
150    #[inline(always)]
151    pub fn variant(&self) -> OC3PE_A {
152        match self.bits {
153            false => OC3PE_A::Disabled,
154            true => OC3PE_A::Enabled,
155        }
156    }
157    ///Checks if the value of the field is `Disabled`
158    #[inline(always)]
159    pub fn is_disabled(&self) -> bool {
160        *self == OC3PE_A::Disabled
161    }
162    ///Checks if the value of the field is `Enabled`
163    #[inline(always)]
164    pub fn is_enabled(&self) -> bool {
165        *self == OC3PE_A::Enabled
166    }
167}
168///Field `OC3PE` writer - desc OC3PE
169pub type OC3PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, OC3PE_A, O>;
170impl<'a, const O: u8> OC3PE_W<'a, O> {
171    ///Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
172    #[inline(always)]
173    pub fn disabled(self) -> &'a mut W {
174        self.variant(OC3PE_A::Disabled)
175    }
176    ///Preload register on CCRx enabled. Preload value is loaded into active register on each update event
177    #[inline(always)]
178    pub fn enabled(self) -> &'a mut W {
179        self.variant(OC3PE_A::Enabled)
180    }
181}
182///Field `OC3M` reader - desc OC3M
183pub type OC3M_R = crate::FieldReader<u8, u8>;
184///Field `OC3M` writer - desc OC3M
185pub type OC3M_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 3, O>;
186///Field `OC3CE` reader - desc OC3CE
187pub type OC3CE_R = crate::BitReader<OC3CE_A>;
188/**desc OC3CE
189
190Value on reset: 0*/
191#[derive(Clone, Copy, Debug, PartialEq, Eq)]
192pub enum OC3CE_A {
193    ///0: Output compare ? clear disabled
194    Disabled = 0,
195    ///1: Output compare ? clear enabled
196    Enabled = 1,
197}
198impl From<OC3CE_A> for bool {
199    #[inline(always)]
200    fn from(variant: OC3CE_A) -> Self {
201        variant as u8 != 0
202    }
203}
204impl OC3CE_R {
205    ///Get enumerated values variant
206    #[inline(always)]
207    pub fn variant(&self) -> OC3CE_A {
208        match self.bits {
209            false => OC3CE_A::Disabled,
210            true => OC3CE_A::Enabled,
211        }
212    }
213    ///Checks if the value of the field is `Disabled`
214    #[inline(always)]
215    pub fn is_disabled(&self) -> bool {
216        *self == OC3CE_A::Disabled
217    }
218    ///Checks if the value of the field is `Enabled`
219    #[inline(always)]
220    pub fn is_enabled(&self) -> bool {
221        *self == OC3CE_A::Enabled
222    }
223}
224///Field `OC3CE` writer - desc OC3CE
225pub type OC3CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, OC3CE_A, O>;
226impl<'a, const O: u8> OC3CE_W<'a, O> {
227    ///Output compare ? clear disabled
228    #[inline(always)]
229    pub fn disabled(self) -> &'a mut W {
230        self.variant(OC3CE_A::Disabled)
231    }
232    ///Output compare ? clear enabled
233    #[inline(always)]
234    pub fn enabled(self) -> &'a mut W {
235        self.variant(OC3CE_A::Enabled)
236    }
237}
238///Field `CC4S` reader - desc CC4S
239pub use CC3S_R as CC4S_R;
240///Field `CC4S` writer - desc CC4S
241pub use CC3S_W as CC4S_W;
242///Field `OC4FE` reader - desc OC4FE
243pub type OC4FE_R = crate::BitReader<bool>;
244///Field `OC4FE` writer - desc OC4FE
245pub type OC4FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
246///Field `OC4PE` reader - desc OC4PE
247pub use OC3PE_R as OC4PE_R;
248///Field `OC4PE` writer - desc OC4PE
249pub use OC3PE_W as OC4PE_W;
250///Field `OC4M` reader - desc OC4M
251pub type OC4M_R = crate::FieldReader<u8, u8>;
252///Field `OC4M` writer - desc OC4M
253pub type OC4M_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, u8, 3, O>;
254///Field `OC4CE` reader - desc OC4CE
255pub use OC3CE_R as OC4CE_R;
256///Field `OC4CE` writer - desc OC4CE
257pub use OC3CE_W as OC4CE_W;
258impl R {
259    ///Bits 0:1 - desc CC3S
260    #[inline(always)]
261    pub fn cc3s(&self) -> CC3S_R {
262        CC3S_R::new((self.bits & 3) as u8)
263    }
264    ///Bit 2 - desc OC3FE
265    #[inline(always)]
266    pub fn oc3fe(&self) -> OC3FE_R {
267        OC3FE_R::new(((self.bits >> 2) & 1) != 0)
268    }
269    ///Bit 3 - desc OC3PE
270    #[inline(always)]
271    pub fn oc3pe(&self) -> OC3PE_R {
272        OC3PE_R::new(((self.bits >> 3) & 1) != 0)
273    }
274    ///Bits 4:6 - desc OC3M
275    #[inline(always)]
276    pub fn oc3m(&self) -> OC3M_R {
277        OC3M_R::new(((self.bits >> 4) & 7) as u8)
278    }
279    ///Bit 7 - desc OC3CE
280    #[inline(always)]
281    pub fn oc3ce(&self) -> OC3CE_R {
282        OC3CE_R::new(((self.bits >> 7) & 1) != 0)
283    }
284    ///Bits 8:9 - desc CC4S
285    #[inline(always)]
286    pub fn cc4s(&self) -> CC4S_R {
287        CC4S_R::new(((self.bits >> 8) & 3) as u8)
288    }
289    ///Bit 10 - desc OC4FE
290    #[inline(always)]
291    pub fn oc4fe(&self) -> OC4FE_R {
292        OC4FE_R::new(((self.bits >> 10) & 1) != 0)
293    }
294    ///Bit 11 - desc OC4PE
295    #[inline(always)]
296    pub fn oc4pe(&self) -> OC4PE_R {
297        OC4PE_R::new(((self.bits >> 11) & 1) != 0)
298    }
299    ///Bits 12:14 - desc OC4M
300    #[inline(always)]
301    pub fn oc4m(&self) -> OC4M_R {
302        OC4M_R::new(((self.bits >> 12) & 7) as u8)
303    }
304    ///Bit 15 - desc OC4CE
305    #[inline(always)]
306    pub fn oc4ce(&self) -> OC4CE_R {
307        OC4CE_R::new(((self.bits >> 15) & 1) != 0)
308    }
309}
310impl W {
311    ///Bits 0:1 - desc CC3S
312    #[inline(always)]
313    #[must_use]
314    pub fn cc3s(&mut self) -> CC3S_W<0> {
315        CC3S_W::new(self)
316    }
317    ///Bit 2 - desc OC3FE
318    #[inline(always)]
319    #[must_use]
320    pub fn oc3fe(&mut self) -> OC3FE_W<2> {
321        OC3FE_W::new(self)
322    }
323    ///Bit 3 - desc OC3PE
324    #[inline(always)]
325    #[must_use]
326    pub fn oc3pe(&mut self) -> OC3PE_W<3> {
327        OC3PE_W::new(self)
328    }
329    ///Bits 4:6 - desc OC3M
330    #[inline(always)]
331    #[must_use]
332    pub fn oc3m(&mut self) -> OC3M_W<4> {
333        OC3M_W::new(self)
334    }
335    ///Bit 7 - desc OC3CE
336    #[inline(always)]
337    #[must_use]
338    pub fn oc3ce(&mut self) -> OC3CE_W<7> {
339        OC3CE_W::new(self)
340    }
341    ///Bits 8:9 - desc CC4S
342    #[inline(always)]
343    #[must_use]
344    pub fn cc4s(&mut self) -> CC4S_W<8> {
345        CC4S_W::new(self)
346    }
347    ///Bit 10 - desc OC4FE
348    #[inline(always)]
349    #[must_use]
350    pub fn oc4fe(&mut self) -> OC4FE_W<10> {
351        OC4FE_W::new(self)
352    }
353    ///Bit 11 - desc OC4PE
354    #[inline(always)]
355    #[must_use]
356    pub fn oc4pe(&mut self) -> OC4PE_W<11> {
357        OC4PE_W::new(self)
358    }
359    ///Bits 12:14 - desc OC4M
360    #[inline(always)]
361    #[must_use]
362    pub fn oc4m(&mut self) -> OC4M_W<12> {
363        OC4M_W::new(self)
364    }
365    ///Bit 15 - desc OC4CE
366    #[inline(always)]
367    #[must_use]
368    pub fn oc4ce(&mut self) -> OC4CE_W<15> {
369        OC4CE_W::new(self)
370    }
371    ///Writes raw bits to the register.
372    #[inline(always)]
373    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
374        self.0.bits(bits);
375        self
376    }
377}
378/**desc CCMR2:OUTPUT
379
380This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
381
382For information about available fields see [ccmr2_output](index.html) module*/
383pub struct CCMR2_OUTPUT_SPEC;
384impl crate::RegisterSpec for CCMR2_OUTPUT_SPEC {
385    type Ux = u32;
386}
387///`read()` method returns [ccmr2_output::R](R) reader structure
388impl crate::Readable for CCMR2_OUTPUT_SPEC {
389    type Reader = R;
390}
391///`write(|w| ..)` method takes [ccmr2_output::W](W) writer structure
392impl crate::Writable for CCMR2_OUTPUT_SPEC {
393    type Writer = W;
394    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
395    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
396}
397///`reset()` method sets CCMR2_OUTPUT to value 0
398impl crate::Resettable for CCMR2_OUTPUT_SPEC {
399    const RESET_VALUE: Self::Ux = 0;
400}
py32f0/py32f040/tim3/ccmr2_output.rs

py32f0/py32f040/tim3/
ccmr2_output.rs
