py32f0/py32f040/tim2/
cr2.rs

1///Register `CR2` reader
2pub struct R(crate::R<CR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR2` writer
17pub struct W(crate::W<CR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CCDS` reader - desc CCDS
38pub type CCDS_R = crate::BitReader<CCDS_A>;
39/**desc CCDS
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum CCDS_A {
44    ///0: CCx DMA request sent when CCx event occurs
45    OnCompare = 0,
46    ///1: CCx DMA request sent when update event occurs
47    OnUpdate = 1,
48}
49impl From<CCDS_A> for bool {
50    #[inline(always)]
51    fn from(variant: CCDS_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl CCDS_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> CCDS_A {
59        match self.bits {
60            false => CCDS_A::OnCompare,
61            true => CCDS_A::OnUpdate,
62        }
63    }
64    ///Checks if the value of the field is `OnCompare`
65    #[inline(always)]
66    pub fn is_on_compare(&self) -> bool {
67        *self == CCDS_A::OnCompare
68    }
69    ///Checks if the value of the field is `OnUpdate`
70    #[inline(always)]
71    pub fn is_on_update(&self) -> bool {
72        *self == CCDS_A::OnUpdate
73    }
74}
75///Field `CCDS` writer - desc CCDS
76pub type CCDS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, CCDS_A, O>;
77impl<'a, const O: u8> CCDS_W<'a, O> {
78    ///CCx DMA request sent when CCx event occurs
79    #[inline(always)]
80    pub fn on_compare(self) -> &'a mut W {
81        self.variant(CCDS_A::OnCompare)
82    }
83    ///CCx DMA request sent when update event occurs
84    #[inline(always)]
85    pub fn on_update(self) -> &'a mut W {
86        self.variant(CCDS_A::OnUpdate)
87    }
88}
89///Field `MMS` reader - desc MMS
90pub type MMS_R = crate::FieldReader<u8, MMS_A>;
91/**desc MMS
92
93Value on reset: 0*/
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95#[repr(u8)]
96pub enum MMS_A {
97    ///0: The UG bit from the TIMx_EGR register is used as trigger output
98    Reset = 0,
99    ///1: The counter enable signal, CNT_EN, is used as trigger output
100    Enable = 1,
101    ///2: The update event is selected as trigger output
102    Update = 2,
103    ///3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
104    ComparePulse = 3,
105    ///4: OC1REF signal is used as trigger output
106    CompareOc1 = 4,
107    ///5: OC2REF signal is used as trigger output
108    CompareOc2 = 5,
109    ///6: OC3REF signal is used as trigger output
110    CompareOc3 = 6,
111    ///7: OC4REF signal is used as trigger output
112    CompareOc4 = 7,
113}
114impl From<MMS_A> for u8 {
115    #[inline(always)]
116    fn from(variant: MMS_A) -> Self {
117        variant as _
118    }
119}
120impl MMS_R {
121    ///Get enumerated values variant
122    #[inline(always)]
123    pub fn variant(&self) -> MMS_A {
124        match self.bits {
125            0 => MMS_A::Reset,
126            1 => MMS_A::Enable,
127            2 => MMS_A::Update,
128            3 => MMS_A::ComparePulse,
129            4 => MMS_A::CompareOc1,
130            5 => MMS_A::CompareOc2,
131            6 => MMS_A::CompareOc3,
132            7 => MMS_A::CompareOc4,
133            _ => unreachable!(),
134        }
135    }
136    ///Checks if the value of the field is `Reset`
137    #[inline(always)]
138    pub fn is_reset(&self) -> bool {
139        *self == MMS_A::Reset
140    }
141    ///Checks if the value of the field is `Enable`
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == MMS_A::Enable
145    }
146    ///Checks if the value of the field is `Update`
147    #[inline(always)]
148    pub fn is_update(&self) -> bool {
149        *self == MMS_A::Update
150    }
151    ///Checks if the value of the field is `ComparePulse`
152    #[inline(always)]
153    pub fn is_compare_pulse(&self) -> bool {
154        *self == MMS_A::ComparePulse
155    }
156    ///Checks if the value of the field is `CompareOc1`
157    #[inline(always)]
158    pub fn is_compare_oc1(&self) -> bool {
159        *self == MMS_A::CompareOc1
160    }
161    ///Checks if the value of the field is `CompareOc2`
162    #[inline(always)]
163    pub fn is_compare_oc2(&self) -> bool {
164        *self == MMS_A::CompareOc2
165    }
166    ///Checks if the value of the field is `CompareOc3`
167    #[inline(always)]
168    pub fn is_compare_oc3(&self) -> bool {
169        *self == MMS_A::CompareOc3
170    }
171    ///Checks if the value of the field is `CompareOc4`
172    #[inline(always)]
173    pub fn is_compare_oc4(&self) -> bool {
174        *self == MMS_A::CompareOc4
175    }
176}
177///Field `MMS` writer - desc MMS
178pub type MMS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, MMS_A, 3, O>;
179impl<'a, const O: u8> MMS_W<'a, O> {
180    ///The UG bit from the TIMx_EGR register is used as trigger output
181    #[inline(always)]
182    pub fn reset(self) -> &'a mut W {
183        self.variant(MMS_A::Reset)
184    }
185    ///The counter enable signal, CNT_EN, is used as trigger output
186    #[inline(always)]
187    pub fn enable(self) -> &'a mut W {
188        self.variant(MMS_A::Enable)
189    }
190    ///The update event is selected as trigger output
191    #[inline(always)]
192    pub fn update(self) -> &'a mut W {
193        self.variant(MMS_A::Update)
194    }
195    ///The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
196    #[inline(always)]
197    pub fn compare_pulse(self) -> &'a mut W {
198        self.variant(MMS_A::ComparePulse)
199    }
200    ///OC1REF signal is used as trigger output
201    #[inline(always)]
202    pub fn compare_oc1(self) -> &'a mut W {
203        self.variant(MMS_A::CompareOc1)
204    }
205    ///OC2REF signal is used as trigger output
206    #[inline(always)]
207    pub fn compare_oc2(self) -> &'a mut W {
208        self.variant(MMS_A::CompareOc2)
209    }
210    ///OC3REF signal is used as trigger output
211    #[inline(always)]
212    pub fn compare_oc3(self) -> &'a mut W {
213        self.variant(MMS_A::CompareOc3)
214    }
215    ///OC4REF signal is used as trigger output
216    #[inline(always)]
217    pub fn compare_oc4(self) -> &'a mut W {
218        self.variant(MMS_A::CompareOc4)
219    }
220}
221///Field `TI1S` reader - desc TI1S
222pub type TI1S_R = crate::BitReader<TI1S_A>;
223/**desc TI1S
224
225Value on reset: 0*/
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum TI1S_A {
228    ///0: TIMx_CH1 pin is connected to TI1 input
229    Single = 0,
230    ///1: TIMx_CH1, CH2, CH3 pins are connected to TI1 input (XOR combination)
231    Xor = 1,
232}
233impl From<TI1S_A> for bool {
234    #[inline(always)]
235    fn from(variant: TI1S_A) -> Self {
236        variant as u8 != 0
237    }
238}
239impl TI1S_R {
240    ///Get enumerated values variant
241    #[inline(always)]
242    pub fn variant(&self) -> TI1S_A {
243        match self.bits {
244            false => TI1S_A::Single,
245            true => TI1S_A::Xor,
246        }
247    }
248    ///Checks if the value of the field is `Single`
249    #[inline(always)]
250    pub fn is_single(&self) -> bool {
251        *self == TI1S_A::Single
252    }
253    ///Checks if the value of the field is `Xor`
254    #[inline(always)]
255    pub fn is_xor(&self) -> bool {
256        *self == TI1S_A::Xor
257    }
258}
259///Field `TI1S` writer - desc TI1S
260pub type TI1S_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, TI1S_A, O>;
261impl<'a, const O: u8> TI1S_W<'a, O> {
262    ///TIMx_CH1 pin is connected to TI1 input
263    #[inline(always)]
264    pub fn single(self) -> &'a mut W {
265        self.variant(TI1S_A::Single)
266    }
267    ///TIMx_CH1, CH2, CH3 pins are connected to TI1 input (XOR combination)
268    #[inline(always)]
269    pub fn xor(self) -> &'a mut W {
270        self.variant(TI1S_A::Xor)
271    }
272}
273impl R {
274    ///Bit 3 - desc CCDS
275    #[inline(always)]
276    pub fn ccds(&self) -> CCDS_R {
277        CCDS_R::new(((self.bits >> 3) & 1) != 0)
278    }
279    ///Bits 4:6 - desc MMS
280    #[inline(always)]
281    pub fn mms(&self) -> MMS_R {
282        MMS_R::new(((self.bits >> 4) & 7) as u8)
283    }
284    ///Bit 7 - desc TI1S
285    #[inline(always)]
286    pub fn ti1s(&self) -> TI1S_R {
287        TI1S_R::new(((self.bits >> 7) & 1) != 0)
288    }
289}
290impl W {
291    ///Bit 3 - desc CCDS
292    #[inline(always)]
293    #[must_use]
294    pub fn ccds(&mut self) -> CCDS_W<3> {
295        CCDS_W::new(self)
296    }
297    ///Bits 4:6 - desc MMS
298    #[inline(always)]
299    #[must_use]
300    pub fn mms(&mut self) -> MMS_W<4> {
301        MMS_W::new(self)
302    }
303    ///Bit 7 - desc TI1S
304    #[inline(always)]
305    #[must_use]
306    pub fn ti1s(&mut self) -> TI1S_W<7> {
307        TI1S_W::new(self)
308    }
309    ///Writes raw bits to the register.
310    #[inline(always)]
311    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
312        self.0.bits(bits);
313        self
314    }
315}
316/**desc CR2
317
318This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
319
320For information about available fields see [cr2](index.html) module*/
321pub struct CR2_SPEC;
322impl crate::RegisterSpec for CR2_SPEC {
323    type Ux = u32;
324}
325///`read()` method returns [cr2::R](R) reader structure
326impl crate::Readable for CR2_SPEC {
327    type Reader = R;
328}
329///`write(|w| ..)` method takes [cr2::W](W) writer structure
330impl crate::Writable for CR2_SPEC {
331    type Writer = W;
332    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
333    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
334}
335///`reset()` method sets CR2 to value 0
336impl crate::Resettable for CR2_SPEC {
337    const RESET_VALUE: Self::Ux = 0;
338}
py32f0/py32f040/tim2/cr2.rs

py32f0/py32f040/tim2/
cr2.rs
