py32f0/py32f040/tim15/
dcr.rs

1///Register `DCR` reader
2pub struct R(crate::R<DCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `DCR` writer
17pub struct W(crate::W<DCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `DBA` reader - desc DBA
38pub type DBA_R = crate::FieldReader<u8, u8>;
39///Field `DBA` writer - desc DBA
40pub type DBA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
41///Field `DBL` reader - desc DBL
42pub type DBL_R = crate::FieldReader<u8, u8>;
43///Field `DBL` writer - desc DBL
44pub type DBL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCR_SPEC, u8, u8, 5, O>;
45impl R {
46    ///Bits 0:4 - desc DBA
47    #[inline(always)]
48    pub fn dba(&self) -> DBA_R {
49        DBA_R::new((self.bits & 0x1f) as u8)
50    }
51    ///Bits 8:12 - desc DBL
52    #[inline(always)]
53    pub fn dbl(&self) -> DBL_R {
54        DBL_R::new(((self.bits >> 8) & 0x1f) as u8)
55    }
56}
57impl W {
58    ///Bits 0:4 - desc DBA
59    #[inline(always)]
60    #[must_use]
61    pub fn dba(&mut self) -> DBA_W<0> {
62        DBA_W::new(self)
63    }
64    ///Bits 8:12 - desc DBL
65    #[inline(always)]
66    #[must_use]
67    pub fn dbl(&mut self) -> DBL_W<8> {
68        DBL_W::new(self)
69    }
70    ///Writes raw bits to the register.
71    #[inline(always)]
72    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
73        self.0.bits(bits);
74        self
75    }
76}
77/**desc DCR
78
79This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
80
81For information about available fields see [dcr](index.html) module*/
82pub struct DCR_SPEC;
83impl crate::RegisterSpec for DCR_SPEC {
84    type Ux = u32;
85}
86///`read()` method returns [dcr::R](R) reader structure
87impl crate::Readable for DCR_SPEC {
88    type Reader = R;
89}
90///`write(|w| ..)` method takes [dcr::W](W) writer structure
91impl crate::Writable for DCR_SPEC {
92    type Writer = W;
93    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
94    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
95}
96///`reset()` method sets DCR to value 0
97impl crate::Resettable for DCR_SPEC {
98    const RESET_VALUE: Self::Ux = 0;
99}
py32f0/py32f040/tim15/dcr.rs

py32f0/py32f040/tim15/
dcr.rs
