py32f0/py32f040/rcc/
ecscr.rs

1///Register `ECSCR` reader
2pub struct R(crate::R<ECSCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ECSCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ECSCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ECSCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `ECSCR` writer
17pub struct W(crate::W<ECSCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ECSCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ECSCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ECSCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `HSE_DRV` reader - HSE_DRV
38pub type HSE_DRV_R = crate::FieldReader<u8, HSE_DRV_A>;
39/**HSE_DRV
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u8)]
44pub enum HSE_DRV_A {
45    ///0: Disable HSE drive
46    Disabled = 0,
47    ///1: Lowest drive
48    Low = 1,
49    ///2: Medium drive
50    Medium = 2,
51    ///3: Highest drive
52    High = 3,
53}
54impl From<HSE_DRV_A> for u8 {
55    #[inline(always)]
56    fn from(variant: HSE_DRV_A) -> Self {
57        variant as _
58    }
59}
60impl HSE_DRV_R {
61    ///Get enumerated values variant
62    #[inline(always)]
63    pub fn variant(&self) -> HSE_DRV_A {
64        match self.bits {
65            0 => HSE_DRV_A::Disabled,
66            1 => HSE_DRV_A::Low,
67            2 => HSE_DRV_A::Medium,
68            3 => HSE_DRV_A::High,
69            _ => unreachable!(),
70        }
71    }
72    ///Checks if the value of the field is `Disabled`
73    #[inline(always)]
74    pub fn is_disabled(&self) -> bool {
75        *self == HSE_DRV_A::Disabled
76    }
77    ///Checks if the value of the field is `Low`
78    #[inline(always)]
79    pub fn is_low(&self) -> bool {
80        *self == HSE_DRV_A::Low
81    }
82    ///Checks if the value of the field is `Medium`
83    #[inline(always)]
84    pub fn is_medium(&self) -> bool {
85        *self == HSE_DRV_A::Medium
86    }
87    ///Checks if the value of the field is `High`
88    #[inline(always)]
89    pub fn is_high(&self) -> bool {
90        *self == HSE_DRV_A::High
91    }
92}
93///Field `HSE_DRV` writer - HSE_DRV
94pub type HSE_DRV_W<'a, const O: u8> =
95    crate::FieldWriterSafe<'a, u32, ECSCR_SPEC, u8, HSE_DRV_A, 2, O>;
96impl<'a, const O: u8> HSE_DRV_W<'a, O> {
97    ///Disable HSE drive
98    #[inline(always)]
99    pub fn disabled(self) -> &'a mut W {
100        self.variant(HSE_DRV_A::Disabled)
101    }
102    ///Lowest drive
103    #[inline(always)]
104    pub fn low(self) -> &'a mut W {
105        self.variant(HSE_DRV_A::Low)
106    }
107    ///Medium drive
108    #[inline(always)]
109    pub fn medium(self) -> &'a mut W {
110        self.variant(HSE_DRV_A::Medium)
111    }
112    ///Highest drive
113    #[inline(always)]
114    pub fn high(self) -> &'a mut W {
115        self.variant(HSE_DRV_A::High)
116    }
117}
118///Field `HSE_STARTUP` reader - HSE_STARTUP
119pub type HSE_STARTUP_R = crate::FieldReader<u8, HSE_STARTUP_A>;
120/**HSE_STARTUP
121
122Value on reset: 0*/
123#[derive(Clone, Copy, Debug, PartialEq, Eq)]
124#[repr(u8)]
125pub enum HSE_STARTUP_A {
126    ///0: HSEBYP=0 4096 LSE clock cycles, HSEBYP=1 2048 LSE clock cycles
127    ClockCycles1 = 0,
128    ///1: HSEBYP=0 2048 LSE clock cycles, HSEBYP=1 1024 LSE clock cycles
129    ClockCycles2 = 1,
130    ///2: HSEBYP=0 8192 LSE clock cycles, HSEBYP=1 4096 LSE clock cycles
131    ClockCycles3 = 2,
132    ///3: Direct Output, regardless of stabilization time
133    DirectOutput = 3,
134}
135impl From<HSE_STARTUP_A> for u8 {
136    #[inline(always)]
137    fn from(variant: HSE_STARTUP_A) -> Self {
138        variant as _
139    }
140}
141impl HSE_STARTUP_R {
142    ///Get enumerated values variant
143    #[inline(always)]
144    pub fn variant(&self) -> HSE_STARTUP_A {
145        match self.bits {
146            0 => HSE_STARTUP_A::ClockCycles1,
147            1 => HSE_STARTUP_A::ClockCycles2,
148            2 => HSE_STARTUP_A::ClockCycles3,
149            3 => HSE_STARTUP_A::DirectOutput,
150            _ => unreachable!(),
151        }
152    }
153    ///Checks if the value of the field is `ClockCycles1`
154    #[inline(always)]
155    pub fn is_clock_cycles1(&self) -> bool {
156        *self == HSE_STARTUP_A::ClockCycles1
157    }
158    ///Checks if the value of the field is `ClockCycles2`
159    #[inline(always)]
160    pub fn is_clock_cycles2(&self) -> bool {
161        *self == HSE_STARTUP_A::ClockCycles2
162    }
163    ///Checks if the value of the field is `ClockCycles3`
164    #[inline(always)]
165    pub fn is_clock_cycles3(&self) -> bool {
166        *self == HSE_STARTUP_A::ClockCycles3
167    }
168    ///Checks if the value of the field is `DirectOutput`
169    #[inline(always)]
170    pub fn is_direct_output(&self) -> bool {
171        *self == HSE_STARTUP_A::DirectOutput
172    }
173}
174///Field `HSE_STARTUP` writer - HSE_STARTUP
175pub type HSE_STARTUP_W<'a, const O: u8> =
176    crate::FieldWriterSafe<'a, u32, ECSCR_SPEC, u8, HSE_STARTUP_A, 2, O>;
177impl<'a, const O: u8> HSE_STARTUP_W<'a, O> {
178    ///HSEBYP=0 4096 LSE clock cycles, HSEBYP=1 2048 LSE clock cycles
179    #[inline(always)]
180    pub fn clock_cycles1(self) -> &'a mut W {
181        self.variant(HSE_STARTUP_A::ClockCycles1)
182    }
183    ///HSEBYP=0 2048 LSE clock cycles, HSEBYP=1 1024 LSE clock cycles
184    #[inline(always)]
185    pub fn clock_cycles2(self) -> &'a mut W {
186        self.variant(HSE_STARTUP_A::ClockCycles2)
187    }
188    ///HSEBYP=0 8192 LSE clock cycles, HSEBYP=1 4096 LSE clock cycles
189    #[inline(always)]
190    pub fn clock_cycles3(self) -> &'a mut W {
191        self.variant(HSE_STARTUP_A::ClockCycles3)
192    }
193    ///Direct Output, regardless of stabilization time
194    #[inline(always)]
195    pub fn direct_output(self) -> &'a mut W {
196        self.variant(HSE_STARTUP_A::DirectOutput)
197    }
198}
199///Field `LSE_DRIVER` reader - LSE clock driver selection
200pub type LSE_DRIVER_R = crate::FieldReader<u8, LSE_DRIVER_A>;
201/**LSE clock driver selection
202
203Value on reset: 0*/
204#[derive(Clone, Copy, Debug, PartialEq, Eq)]
205#[repr(u8)]
206pub enum LSE_DRIVER_A {
207    ///0: Disable LSE drive
208    Disabled = 0,
209    ///1: Lowest drive
210    Low = 1,
211    ///2: Medium drive
212    Medium = 2,
213    ///3: Highest drive
214    High = 3,
215}
216impl From<LSE_DRIVER_A> for u8 {
217    #[inline(always)]
218    fn from(variant: LSE_DRIVER_A) -> Self {
219        variant as _
220    }
221}
222impl LSE_DRIVER_R {
223    ///Get enumerated values variant
224    #[inline(always)]
225    pub fn variant(&self) -> LSE_DRIVER_A {
226        match self.bits {
227            0 => LSE_DRIVER_A::Disabled,
228            1 => LSE_DRIVER_A::Low,
229            2 => LSE_DRIVER_A::Medium,
230            3 => LSE_DRIVER_A::High,
231            _ => unreachable!(),
232        }
233    }
234    ///Checks if the value of the field is `Disabled`
235    #[inline(always)]
236    pub fn is_disabled(&self) -> bool {
237        *self == LSE_DRIVER_A::Disabled
238    }
239    ///Checks if the value of the field is `Low`
240    #[inline(always)]
241    pub fn is_low(&self) -> bool {
242        *self == LSE_DRIVER_A::Low
243    }
244    ///Checks if the value of the field is `Medium`
245    #[inline(always)]
246    pub fn is_medium(&self) -> bool {
247        *self == LSE_DRIVER_A::Medium
248    }
249    ///Checks if the value of the field is `High`
250    #[inline(always)]
251    pub fn is_high(&self) -> bool {
252        *self == LSE_DRIVER_A::High
253    }
254}
255///Field `LSE_DRIVER` writer - LSE clock driver selection
256pub type LSE_DRIVER_W<'a, const O: u8> =
257    crate::FieldWriterSafe<'a, u32, ECSCR_SPEC, u8, LSE_DRIVER_A, 2, O>;
258impl<'a, const O: u8> LSE_DRIVER_W<'a, O> {
259    ///Disable LSE drive
260    #[inline(always)]
261    pub fn disabled(self) -> &'a mut W {
262        self.variant(LSE_DRIVER_A::Disabled)
263    }
264    ///Lowest drive
265    #[inline(always)]
266    pub fn low(self) -> &'a mut W {
267        self.variant(LSE_DRIVER_A::Low)
268    }
269    ///Medium drive
270    #[inline(always)]
271    pub fn medium(self) -> &'a mut W {
272        self.variant(LSE_DRIVER_A::Medium)
273    }
274    ///Highest drive
275    #[inline(always)]
276    pub fn high(self) -> &'a mut W {
277        self.variant(LSE_DRIVER_A::High)
278    }
279}
280///Field `LSE_STARTUP` reader - LSE_STARTUP
281pub type LSE_STARTUP_R = crate::FieldReader<u8, LSE_STARTUP_A>;
282/**LSE_STARTUP
283
284Value on reset: 0*/
285#[derive(Clone, Copy, Debug, PartialEq, Eq)]
286#[repr(u8)]
287pub enum LSE_STARTUP_A {
288    ///0: LSEBYP=0 4096 LSE clock cycles, LSEBYP=1 2048 LSE clock cycles
289    ClockCycles1 = 0,
290    ///1: LSEBYP=0 2048 LSE clock cycles, LSEBYP=1 1024 LSE clock cycles
291    ClockCycles2 = 1,
292    ///2: LSEBYP=0 8192 LSE clock cycles, LSEBYP=1 4096 LSE clock cycles
293    ClockCycles3 = 2,
294    ///3: Direct Output, regardless of stabilization time
295    DirectOutput = 3,
296}
297impl From<LSE_STARTUP_A> for u8 {
298    #[inline(always)]
299    fn from(variant: LSE_STARTUP_A) -> Self {
300        variant as _
301    }
302}
303impl LSE_STARTUP_R {
304    ///Get enumerated values variant
305    #[inline(always)]
306    pub fn variant(&self) -> LSE_STARTUP_A {
307        match self.bits {
308            0 => LSE_STARTUP_A::ClockCycles1,
309            1 => LSE_STARTUP_A::ClockCycles2,
310            2 => LSE_STARTUP_A::ClockCycles3,
311            3 => LSE_STARTUP_A::DirectOutput,
312            _ => unreachable!(),
313        }
314    }
315    ///Checks if the value of the field is `ClockCycles1`
316    #[inline(always)]
317    pub fn is_clock_cycles1(&self) -> bool {
318        *self == LSE_STARTUP_A::ClockCycles1
319    }
320    ///Checks if the value of the field is `ClockCycles2`
321    #[inline(always)]
322    pub fn is_clock_cycles2(&self) -> bool {
323        *self == LSE_STARTUP_A::ClockCycles2
324    }
325    ///Checks if the value of the field is `ClockCycles3`
326    #[inline(always)]
327    pub fn is_clock_cycles3(&self) -> bool {
328        *self == LSE_STARTUP_A::ClockCycles3
329    }
330    ///Checks if the value of the field is `DirectOutput`
331    #[inline(always)]
332    pub fn is_direct_output(&self) -> bool {
333        *self == LSE_STARTUP_A::DirectOutput
334    }
335}
336///Field `LSE_STARTUP` writer - LSE_STARTUP
337pub type LSE_STARTUP_W<'a, const O: u8> =
338    crate::FieldWriterSafe<'a, u32, ECSCR_SPEC, u8, LSE_STARTUP_A, 2, O>;
339impl<'a, const O: u8> LSE_STARTUP_W<'a, O> {
340    ///LSEBYP=0 4096 LSE clock cycles, LSEBYP=1 2048 LSE clock cycles
341    #[inline(always)]
342    pub fn clock_cycles1(self) -> &'a mut W {
343        self.variant(LSE_STARTUP_A::ClockCycles1)
344    }
345    ///LSEBYP=0 2048 LSE clock cycles, LSEBYP=1 1024 LSE clock cycles
346    #[inline(always)]
347    pub fn clock_cycles2(self) -> &'a mut W {
348        self.variant(LSE_STARTUP_A::ClockCycles2)
349    }
350    ///LSEBYP=0 8192 LSE clock cycles, LSEBYP=1 4096 LSE clock cycles
351    #[inline(always)]
352    pub fn clock_cycles3(self) -> &'a mut W {
353        self.variant(LSE_STARTUP_A::ClockCycles3)
354    }
355    ///Direct Output, regardless of stabilization time
356    #[inline(always)]
357    pub fn direct_output(self) -> &'a mut W {
358        self.variant(LSE_STARTUP_A::DirectOutput)
359    }
360}
361impl R {
362    ///Bits 0:1 - HSE_DRV
363    #[inline(always)]
364    pub fn hse_drv(&self) -> HSE_DRV_R {
365        HSE_DRV_R::new((self.bits & 3) as u8)
366    }
367    ///Bits 3:4 - HSE_STARTUP
368    #[inline(always)]
369    pub fn hse_startup(&self) -> HSE_STARTUP_R {
370        HSE_STARTUP_R::new(((self.bits >> 3) & 3) as u8)
371    }
372    ///Bits 16:17 - LSE clock driver selection
373    #[inline(always)]
374    pub fn lse_driver(&self) -> LSE_DRIVER_R {
375        LSE_DRIVER_R::new(((self.bits >> 16) & 3) as u8)
376    }
377    ///Bits 20:21 - LSE_STARTUP
378    #[inline(always)]
379    pub fn lse_startup(&self) -> LSE_STARTUP_R {
380        LSE_STARTUP_R::new(((self.bits >> 20) & 3) as u8)
381    }
382}
383impl W {
384    ///Bits 0:1 - HSE_DRV
385    #[inline(always)]
386    #[must_use]
387    pub fn hse_drv(&mut self) -> HSE_DRV_W<0> {
388        HSE_DRV_W::new(self)
389    }
390    ///Bits 3:4 - HSE_STARTUP
391    #[inline(always)]
392    #[must_use]
393    pub fn hse_startup(&mut self) -> HSE_STARTUP_W<3> {
394        HSE_STARTUP_W::new(self)
395    }
396    ///Bits 16:17 - LSE clock driver selection
397    #[inline(always)]
398    #[must_use]
399    pub fn lse_driver(&mut self) -> LSE_DRIVER_W<16> {
400        LSE_DRIVER_W::new(self)
401    }
402    ///Bits 20:21 - LSE_STARTUP
403    #[inline(always)]
404    #[must_use]
405    pub fn lse_startup(&mut self) -> LSE_STARTUP_W<20> {
406        LSE_STARTUP_W::new(self)
407    }
408    ///Writes raw bits to the register.
409    #[inline(always)]
410    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
411        self.0.bits(bits);
412        self
413    }
414}
415/**External clock source control register
416
417This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
418
419For information about available fields see [ecscr](index.html) module*/
420pub struct ECSCR_SPEC;
421impl crate::RegisterSpec for ECSCR_SPEC {
422    type Ux = u32;
423}
424///`read()` method returns [ecscr::R](R) reader structure
425impl crate::Readable for ECSCR_SPEC {
426    type Reader = R;
427}
428///`write(|w| ..)` method takes [ecscr::W](W) writer structure
429impl crate::Writable for ECSCR_SPEC {
430    type Writer = W;
431    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
432    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
433}
434///`reset()` method sets ECSCR to value 0
435impl crate::Resettable for ECSCR_SPEC {
436    const RESET_VALUE: Self::Ux = 0;
437}
py32f0/py32f040/rcc/ecscr.rs

py32f0/py32f040/rcc/
ecscr.rs
