py32f0/py32f040/rcc/
cicr.rs

1///Register `CICR` writer
2pub struct W(crate::W<CICR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CICR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CICR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CICR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22/**LSI ready interrupt clear
23
24Value on reset: 0*/
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum LSIRDYCW_AW {
27    ///1: Clear interrupt flag
28    Clear = 1,
29}
30impl From<LSIRDYCW_AW> for bool {
31    #[inline(always)]
32    fn from(variant: LSIRDYCW_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36///Field `LSIRDYC` writer - LSI ready interrupt clear
37pub type LSIRDYC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CICR_SPEC, LSIRDYCW_AW, O>;
38impl<'a, const O: u8> LSIRDYC_W<'a, O> {
39    ///Clear interrupt flag
40    #[inline(always)]
41    pub fn clear(self) -> &'a mut W {
42        self.variant(LSIRDYCW_AW::Clear)
43    }
44}
45///Field `LSERDYC` writer - LSE ready interrupt clear
46pub use LSIRDYC_W as LSERDYC_W;
47///Field `HSIRDYC` writer - HSI ready interrupt clear
48pub use LSIRDYC_W as HSIRDYC_W;
49///Field `HSERDYC` writer - HSE ready interrupt clear
50pub use LSIRDYC_W as HSERDYC_W;
51///Field `PLLRDYC` writer - PLL ready interrupt clear
52pub use LSIRDYC_W as PLLRDYC_W;
53///Field `CSSC` writer - clock secure system interrupt flag clear
54pub type CSSC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CICR_SPEC, bool, O>;
55/**LSE clock secure system interrupt flag clear
56
57Value on reset: 0*/
58#[derive(Clone, Copy, Debug, PartialEq, Eq)]
59pub enum LSECSSCW_AW {
60    ///1: Clear LSE clock secure system interrupt flag
61    Clear = 1,
62}
63impl From<LSECSSCW_AW> for bool {
64    #[inline(always)]
65    fn from(variant: LSECSSCW_AW) -> Self {
66        variant as u8 != 0
67    }
68}
69///Field `LSECSSC` writer - LSE clock secure system interrupt flag clear
70pub type LSECSSC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CICR_SPEC, LSECSSCW_AW, O>;
71impl<'a, const O: u8> LSECSSC_W<'a, O> {
72    ///Clear LSE clock secure system interrupt flag
73    #[inline(always)]
74    pub fn clear(self) -> &'a mut W {
75        self.variant(LSECSSCW_AW::Clear)
76    }
77}
78impl W {
79    ///Bit 0 - LSI ready interrupt clear
80    #[inline(always)]
81    #[must_use]
82    pub fn lsirdyc(&mut self) -> LSIRDYC_W<0> {
83        LSIRDYC_W::new(self)
84    }
85    ///Bit 1 - LSE ready interrupt clear
86    #[inline(always)]
87    #[must_use]
88    pub fn lserdyc(&mut self) -> LSERDYC_W<1> {
89        LSERDYC_W::new(self)
90    }
91    ///Bit 3 - HSI ready interrupt clear
92    #[inline(always)]
93    #[must_use]
94    pub fn hsirdyc(&mut self) -> HSIRDYC_W<3> {
95        HSIRDYC_W::new(self)
96    }
97    ///Bit 4 - HSE ready interrupt clear
98    #[inline(always)]
99    #[must_use]
100    pub fn hserdyc(&mut self) -> HSERDYC_W<4> {
101        HSERDYC_W::new(self)
102    }
103    ///Bit 5 - PLL ready interrupt clear
104    #[inline(always)]
105    #[must_use]
106    pub fn pllrdyc(&mut self) -> PLLRDYC_W<5> {
107        PLLRDYC_W::new(self)
108    }
109    ///Bit 8 - clock secure system interrupt flag clear
110    #[inline(always)]
111    #[must_use]
112    pub fn cssc(&mut self) -> CSSC_W<8> {
113        CSSC_W::new(self)
114    }
115    ///Bit 9 - LSE clock secure system interrupt flag clear
116    #[inline(always)]
117    #[must_use]
118    pub fn lsecssc(&mut self) -> LSECSSC_W<9> {
119        LSECSSC_W::new(self)
120    }
121    ///Writes raw bits to the register.
122    #[inline(always)]
123    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
124        self.0.bits(bits);
125        self
126    }
127}
128/**Clock interrupt clear register
129
130This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
131
132For information about available fields see [cicr](index.html) module*/
133pub struct CICR_SPEC;
134impl crate::RegisterSpec for CICR_SPEC {
135    type Ux = u32;
136}
137///`write(|w| ..)` method takes [cicr::W](W) writer structure
138impl crate::Writable for CICR_SPEC {
139    type Writer = W;
140    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
141    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
142}
143///`reset()` method sets CICR to value 0
144impl crate::Resettable for CICR_SPEC {
145    const RESET_VALUE: Self::Ux = 0;
146}
py32f0/py32f040/rcc/cicr.rs

py32f0/py32f040/rcc/
cicr.rs
