py32f0/py32f040/dbg/
apb_fz2.rs

1///Register `APB_FZ2` reader
2pub struct R(crate::R<APB_FZ2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<APB_FZ2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<APB_FZ2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<APB_FZ2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `APB_FZ2` writer
17pub struct W(crate::W<APB_FZ2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<APB_FZ2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<APB_FZ2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<APB_FZ2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `DBG_TIMER1_STOP` reader - Debug Timer 1 stopped when Core is halted
38pub type DBG_TIMER1_STOP_R = crate::BitReader<DBG_TIMER1_STOP_A>;
39/**Debug Timer 1 stopped when Core is halted
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum DBG_TIMER1_STOP_A {
44    ///0: The counter clock of TIMx is fed even if the core is halted
45    Continue = 0,
46    ///1: The counter clock of TIMx is stopped when the core is halted
47    Stop = 1,
48}
49impl From<DBG_TIMER1_STOP_A> for bool {
50    #[inline(always)]
51    fn from(variant: DBG_TIMER1_STOP_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl DBG_TIMER1_STOP_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> DBG_TIMER1_STOP_A {
59        match self.bits {
60            false => DBG_TIMER1_STOP_A::Continue,
61            true => DBG_TIMER1_STOP_A::Stop,
62        }
63    }
64    ///Checks if the value of the field is `Continue`
65    #[inline(always)]
66    pub fn is_continue(&self) -> bool {
67        *self == DBG_TIMER1_STOP_A::Continue
68    }
69    ///Checks if the value of the field is `Stop`
70    #[inline(always)]
71    pub fn is_stop(&self) -> bool {
72        *self == DBG_TIMER1_STOP_A::Stop
73    }
74}
75///Field `DBG_TIMER1_STOP` writer - Debug Timer 1 stopped when Core is halted
76pub type DBG_TIMER1_STOP_W<'a, const O: u8> =
77    crate::BitWriter<'a, u32, APB_FZ2_SPEC, DBG_TIMER1_STOP_A, O>;
78impl<'a, const O: u8> DBG_TIMER1_STOP_W<'a, O> {
79    ///The counter clock of TIMx is fed even if the core is halted
80    #[inline(always)]
81    pub fn continue_(self) -> &'a mut W {
82        self.variant(DBG_TIMER1_STOP_A::Continue)
83    }
84    ///The counter clock of TIMx is stopped when the core is halted
85    #[inline(always)]
86    pub fn stop(self) -> &'a mut W {
87        self.variant(DBG_TIMER1_STOP_A::Stop)
88    }
89}
90///Field `DBG_TIMER14_STOP` reader - Debug Timer 14 stopped when Core is halted
91pub use DBG_TIMER1_STOP_R as DBG_TIMER14_STOP_R;
92///Field `DBG_TIMER15_STOP` reader - Debug Timer 15 stopped when Core is halted
93pub use DBG_TIMER1_STOP_R as DBG_TIMER15_STOP_R;
94///Field `DBG_TIMER16_STOP` reader - Debug Timer 16 stopped when Core is halted
95pub use DBG_TIMER1_STOP_R as DBG_TIMER16_STOP_R;
96///Field `DBG_TIMER17_STOP` reader - Debug Timer 17 stopped when Core is halted
97pub use DBG_TIMER1_STOP_R as DBG_TIMER17_STOP_R;
98///Field `DBG_TIMER14_STOP` writer - Debug Timer 14 stopped when Core is halted
99pub use DBG_TIMER1_STOP_W as DBG_TIMER14_STOP_W;
100///Field `DBG_TIMER15_STOP` writer - Debug Timer 15 stopped when Core is halted
101pub use DBG_TIMER1_STOP_W as DBG_TIMER15_STOP_W;
102///Field `DBG_TIMER16_STOP` writer - Debug Timer 16 stopped when Core is halted
103pub use DBG_TIMER1_STOP_W as DBG_TIMER16_STOP_W;
104///Field `DBG_TIMER17_STOP` writer - Debug Timer 17 stopped when Core is halted
105pub use DBG_TIMER1_STOP_W as DBG_TIMER17_STOP_W;
106impl R {
107    ///Bit 11 - Debug Timer 1 stopped when Core is halted
108    #[inline(always)]
109    pub fn dbg_timer1_stop(&self) -> DBG_TIMER1_STOP_R {
110        DBG_TIMER1_STOP_R::new(((self.bits >> 11) & 1) != 0)
111    }
112    ///Bit 15 - Debug Timer 14 stopped when Core is halted
113    #[inline(always)]
114    pub fn dbg_timer14_stop(&self) -> DBG_TIMER14_STOP_R {
115        DBG_TIMER14_STOP_R::new(((self.bits >> 15) & 1) != 0)
116    }
117    ///Bit 16 - Debug Timer 15 stopped when Core is halted
118    #[inline(always)]
119    pub fn dbg_timer15_stop(&self) -> DBG_TIMER15_STOP_R {
120        DBG_TIMER15_STOP_R::new(((self.bits >> 16) & 1) != 0)
121    }
122    ///Bit 17 - Debug Timer 16 stopped when Core is halted
123    #[inline(always)]
124    pub fn dbg_timer16_stop(&self) -> DBG_TIMER16_STOP_R {
125        DBG_TIMER16_STOP_R::new(((self.bits >> 17) & 1) != 0)
126    }
127    ///Bit 18 - Debug Timer 17 stopped when Core is halted
128    #[inline(always)]
129    pub fn dbg_timer17_stop(&self) -> DBG_TIMER17_STOP_R {
130        DBG_TIMER17_STOP_R::new(((self.bits >> 18) & 1) != 0)
131    }
132}
133impl W {
134    ///Bit 11 - Debug Timer 1 stopped when Core is halted
135    #[inline(always)]
136    #[must_use]
137    pub fn dbg_timer1_stop(&mut self) -> DBG_TIMER1_STOP_W<11> {
138        DBG_TIMER1_STOP_W::new(self)
139    }
140    ///Bit 15 - Debug Timer 14 stopped when Core is halted
141    #[inline(always)]
142    #[must_use]
143    pub fn dbg_timer14_stop(&mut self) -> DBG_TIMER14_STOP_W<15> {
144        DBG_TIMER14_STOP_W::new(self)
145    }
146    ///Bit 16 - Debug Timer 15 stopped when Core is halted
147    #[inline(always)]
148    #[must_use]
149    pub fn dbg_timer15_stop(&mut self) -> DBG_TIMER15_STOP_W<16> {
150        DBG_TIMER15_STOP_W::new(self)
151    }
152    ///Bit 17 - Debug Timer 16 stopped when Core is halted
153    #[inline(always)]
154    #[must_use]
155    pub fn dbg_timer16_stop(&mut self) -> DBG_TIMER16_STOP_W<17> {
156        DBG_TIMER16_STOP_W::new(self)
157    }
158    ///Bit 18 - Debug Timer 17 stopped when Core is halted
159    #[inline(always)]
160    #[must_use]
161    pub fn dbg_timer17_stop(&mut self) -> DBG_TIMER17_STOP_W<18> {
162        DBG_TIMER17_STOP_W::new(self)
163    }
164    ///Writes raw bits to the register.
165    #[inline(always)]
166    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
167        self.0.bits(bits);
168        self
169    }
170}
171/**APB Freeze Register2
172
173This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
174
175For information about available fields see [apb_fz2](index.html) module*/
176pub struct APB_FZ2_SPEC;
177impl crate::RegisterSpec for APB_FZ2_SPEC {
178    type Ux = u32;
179}
180///`read()` method returns [apb_fz2::R](R) reader structure
181impl crate::Readable for APB_FZ2_SPEC {
182    type Reader = R;
183}
184///`write(|w| ..)` method takes [apb_fz2::W](W) writer structure
185impl crate::Writable for APB_FZ2_SPEC {
186    type Writer = W;
187    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
188    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
189}
190///`reset()` method sets APB_FZ2 to value 0
191impl crate::Resettable for APB_FZ2_SPEC {
192    const RESET_VALUE: Self::Ux = 0;
193}
py32f0/py32f040/dbg/apb_fz2.rs

py32f0/py32f040/dbg/
apb_fz2.rs
