py32f0/py32f030/usart1/
cr2.rs

1///Register `CR2` reader
2pub struct R(crate::R<CR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR2` writer
17pub struct W(crate::W<CR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `ADD` reader - Address of the USART node
38pub type ADD_R = crate::FieldReader<u8, u8>;
39///Field `ADD` writer - Address of the USART node
40pub type ADD_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, u8, 4, O>;
41///Field `LBCL` reader - Last bit clock pulse
42pub type LBCL_R = crate::BitReader<LBCL_A>;
43/**Last bit clock pulse
44
45Value on reset: 0*/
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum LBCL_A {
48    ///0: The clock pulse of the last data bit is not output to the CK pin
49    NotOutput = 0,
50    ///1: The clock pulse of the last data bit is output to the CK pin
51    Output = 1,
52}
53impl From<LBCL_A> for bool {
54    #[inline(always)]
55    fn from(variant: LBCL_A) -> Self {
56        variant as u8 != 0
57    }
58}
59impl LBCL_R {
60    ///Get enumerated values variant
61    #[inline(always)]
62    pub fn variant(&self) -> LBCL_A {
63        match self.bits {
64            false => LBCL_A::NotOutput,
65            true => LBCL_A::Output,
66        }
67    }
68    ///Checks if the value of the field is `NotOutput`
69    #[inline(always)]
70    pub fn is_not_output(&self) -> bool {
71        *self == LBCL_A::NotOutput
72    }
73    ///Checks if the value of the field is `Output`
74    #[inline(always)]
75    pub fn is_output(&self) -> bool {
76        *self == LBCL_A::Output
77    }
78}
79///Field `LBCL` writer - Last bit clock pulse
80pub type LBCL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, LBCL_A, O>;
81impl<'a, const O: u8> LBCL_W<'a, O> {
82    ///The clock pulse of the last data bit is not output to the CK pin
83    #[inline(always)]
84    pub fn not_output(self) -> &'a mut W {
85        self.variant(LBCL_A::NotOutput)
86    }
87    ///The clock pulse of the last data bit is output to the CK pin
88    #[inline(always)]
89    pub fn output(self) -> &'a mut W {
90        self.variant(LBCL_A::Output)
91    }
92}
93///Field `CPHA` reader - Clock phase
94pub type CPHA_R = crate::BitReader<CPHA_A>;
95/**Clock phase
96
97Value on reset: 0*/
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99pub enum CPHA_A {
100    ///0: The first clock transition is the first data capture edge
101    First = 0,
102    ///1: The second clock transition is the first data capture edge
103    Second = 1,
104}
105impl From<CPHA_A> for bool {
106    #[inline(always)]
107    fn from(variant: CPHA_A) -> Self {
108        variant as u8 != 0
109    }
110}
111impl CPHA_R {
112    ///Get enumerated values variant
113    #[inline(always)]
114    pub fn variant(&self) -> CPHA_A {
115        match self.bits {
116            false => CPHA_A::First,
117            true => CPHA_A::Second,
118        }
119    }
120    ///Checks if the value of the field is `First`
121    #[inline(always)]
122    pub fn is_first(&self) -> bool {
123        *self == CPHA_A::First
124    }
125    ///Checks if the value of the field is `Second`
126    #[inline(always)]
127    pub fn is_second(&self) -> bool {
128        *self == CPHA_A::Second
129    }
130}
131///Field `CPHA` writer - Clock phase
132pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, CPHA_A, O>;
133impl<'a, const O: u8> CPHA_W<'a, O> {
134    ///The first clock transition is the first data capture edge
135    #[inline(always)]
136    pub fn first(self) -> &'a mut W {
137        self.variant(CPHA_A::First)
138    }
139    ///The second clock transition is the first data capture edge
140    #[inline(always)]
141    pub fn second(self) -> &'a mut W {
142        self.variant(CPHA_A::Second)
143    }
144}
145///Field `CPOL` reader - Clock polarity
146pub type CPOL_R = crate::BitReader<CPOL_A>;
147/**Clock polarity
148
149Value on reset: 0*/
150#[derive(Clone, Copy, Debug, PartialEq, Eq)]
151pub enum CPOL_A {
152    ///0: Steady low value on CK pin outside transmission window
153    Low = 0,
154    ///1: Steady high value on CK pin outside transmission window
155    High = 1,
156}
157impl From<CPOL_A> for bool {
158    #[inline(always)]
159    fn from(variant: CPOL_A) -> Self {
160        variant as u8 != 0
161    }
162}
163impl CPOL_R {
164    ///Get enumerated values variant
165    #[inline(always)]
166    pub fn variant(&self) -> CPOL_A {
167        match self.bits {
168            false => CPOL_A::Low,
169            true => CPOL_A::High,
170        }
171    }
172    ///Checks if the value of the field is `Low`
173    #[inline(always)]
174    pub fn is_low(&self) -> bool {
175        *self == CPOL_A::Low
176    }
177    ///Checks if the value of the field is `High`
178    #[inline(always)]
179    pub fn is_high(&self) -> bool {
180        *self == CPOL_A::High
181    }
182}
183///Field `CPOL` writer - Clock polarity
184pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, CPOL_A, O>;
185impl<'a, const O: u8> CPOL_W<'a, O> {
186    ///Steady low value on CK pin outside transmission window
187    #[inline(always)]
188    pub fn low(self) -> &'a mut W {
189        self.variant(CPOL_A::Low)
190    }
191    ///Steady high value on CK pin outside transmission window
192    #[inline(always)]
193    pub fn high(self) -> &'a mut W {
194        self.variant(CPOL_A::High)
195    }
196}
197///Field `CLKEN` reader - Clock enable
198pub type CLKEN_R = crate::BitReader<CLKEN_A>;
199/**Clock enable
200
201Value on reset: 0*/
202#[derive(Clone, Copy, Debug, PartialEq, Eq)]
203pub enum CLKEN_A {
204    ///0: CK pin disabled
205    Disabled = 0,
206    ///1: CK pin enabled
207    Enabled = 1,
208}
209impl From<CLKEN_A> for bool {
210    #[inline(always)]
211    fn from(variant: CLKEN_A) -> Self {
212        variant as u8 != 0
213    }
214}
215impl CLKEN_R {
216    ///Get enumerated values variant
217    #[inline(always)]
218    pub fn variant(&self) -> CLKEN_A {
219        match self.bits {
220            false => CLKEN_A::Disabled,
221            true => CLKEN_A::Enabled,
222        }
223    }
224    ///Checks if the value of the field is `Disabled`
225    #[inline(always)]
226    pub fn is_disabled(&self) -> bool {
227        *self == CLKEN_A::Disabled
228    }
229    ///Checks if the value of the field is `Enabled`
230    #[inline(always)]
231    pub fn is_enabled(&self) -> bool {
232        *self == CLKEN_A::Enabled
233    }
234}
235///Field `CLKEN` writer - Clock enable
236pub type CLKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, CLKEN_A, O>;
237impl<'a, const O: u8> CLKEN_W<'a, O> {
238    ///CK pin disabled
239    #[inline(always)]
240    pub fn disabled(self) -> &'a mut W {
241        self.variant(CLKEN_A::Disabled)
242    }
243    ///CK pin enabled
244    #[inline(always)]
245    pub fn enabled(self) -> &'a mut W {
246        self.variant(CLKEN_A::Enabled)
247    }
248}
249///Field `STOP` reader - STOP bits
250pub type STOP_R = crate::FieldReader<u8, STOP_A>;
251/**STOP bits
252
253Value on reset: 0*/
254#[derive(Clone, Copy, Debug, PartialEq, Eq)]
255#[repr(u8)]
256pub enum STOP_A {
257    ///0: 1 stop bit
258    Stop1 = 0,
259    ///1: 2 stop bits
260    Stop2 = 1,
261}
262impl From<STOP_A> for u8 {
263    #[inline(always)]
264    fn from(variant: STOP_A) -> Self {
265        variant as _
266    }
267}
268impl STOP_R {
269    ///Get enumerated values variant
270    #[inline(always)]
271    pub fn variant(&self) -> Option<STOP_A> {
272        match self.bits {
273            0 => Some(STOP_A::Stop1),
274            1 => Some(STOP_A::Stop2),
275            _ => None,
276        }
277    }
278    ///Checks if the value of the field is `Stop1`
279    #[inline(always)]
280    pub fn is_stop1(&self) -> bool {
281        *self == STOP_A::Stop1
282    }
283    ///Checks if the value of the field is `Stop2`
284    #[inline(always)]
285    pub fn is_stop2(&self) -> bool {
286        *self == STOP_A::Stop2
287    }
288}
289///Field `STOP` writer - STOP bits
290pub type STOP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR2_SPEC, u8, STOP_A, 2, O>;
291impl<'a, const O: u8> STOP_W<'a, O> {
292    ///1 stop bit
293    #[inline(always)]
294    pub fn stop1(self) -> &'a mut W {
295        self.variant(STOP_A::Stop1)
296    }
297    ///2 stop bits
298    #[inline(always)]
299    pub fn stop2(self) -> &'a mut W {
300        self.variant(STOP_A::Stop2)
301    }
302}
303impl R {
304    ///Bits 0:3 - Address of the USART node
305    #[inline(always)]
306    pub fn add(&self) -> ADD_R {
307        ADD_R::new((self.bits & 0x0f) as u8)
308    }
309    ///Bit 8 - Last bit clock pulse
310    #[inline(always)]
311    pub fn lbcl(&self) -> LBCL_R {
312        LBCL_R::new(((self.bits >> 8) & 1) != 0)
313    }
314    ///Bit 9 - Clock phase
315    #[inline(always)]
316    pub fn cpha(&self) -> CPHA_R {
317        CPHA_R::new(((self.bits >> 9) & 1) != 0)
318    }
319    ///Bit 10 - Clock polarity
320    #[inline(always)]
321    pub fn cpol(&self) -> CPOL_R {
322        CPOL_R::new(((self.bits >> 10) & 1) != 0)
323    }
324    ///Bit 11 - Clock enable
325    #[inline(always)]
326    pub fn clken(&self) -> CLKEN_R {
327        CLKEN_R::new(((self.bits >> 11) & 1) != 0)
328    }
329    ///Bits 12:13 - STOP bits
330    #[inline(always)]
331    pub fn stop(&self) -> STOP_R {
332        STOP_R::new(((self.bits >> 12) & 3) as u8)
333    }
334}
335impl W {
336    ///Bits 0:3 - Address of the USART node
337    #[inline(always)]
338    #[must_use]
339    pub fn add(&mut self) -> ADD_W<0> {
340        ADD_W::new(self)
341    }
342    ///Bit 8 - Last bit clock pulse
343    #[inline(always)]
344    #[must_use]
345    pub fn lbcl(&mut self) -> LBCL_W<8> {
346        LBCL_W::new(self)
347    }
348    ///Bit 9 - Clock phase
349    #[inline(always)]
350    #[must_use]
351    pub fn cpha(&mut self) -> CPHA_W<9> {
352        CPHA_W::new(self)
353    }
354    ///Bit 10 - Clock polarity
355    #[inline(always)]
356    #[must_use]
357    pub fn cpol(&mut self) -> CPOL_W<10> {
358        CPOL_W::new(self)
359    }
360    ///Bit 11 - Clock enable
361    #[inline(always)]
362    #[must_use]
363    pub fn clken(&mut self) -> CLKEN_W<11> {
364        CLKEN_W::new(self)
365    }
366    ///Bits 12:13 - STOP bits
367    #[inline(always)]
368    #[must_use]
369    pub fn stop(&mut self) -> STOP_W<12> {
370        STOP_W::new(self)
371    }
372    ///Writes raw bits to the register.
373    #[inline(always)]
374    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
375        self.0.bits(bits);
376        self
377    }
378}
379/**Control register 2
380
381This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
382
383For information about available fields see [cr2](index.html) module*/
384pub struct CR2_SPEC;
385impl crate::RegisterSpec for CR2_SPEC {
386    type Ux = u32;
387}
388///`read()` method returns [cr2::R](R) reader structure
389impl crate::Readable for CR2_SPEC {
390    type Reader = R;
391}
392///`write(|w| ..)` method takes [cr2::W](W) writer structure
393impl crate::Writable for CR2_SPEC {
394    type Writer = W;
395    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
396    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
397}
398///`reset()` method sets CR2 to value 0
399impl crate::Resettable for CR2_SPEC {
400    const RESET_VALUE: Self::Ux = 0;
401}
py32f0/py32f030/usart1/cr2.rs

py32f0/py32f030/usart1/
cr2.rs
