py32f0/py32f030/tim14/
egr.rs

1///Register `EGR` writer
2pub struct W(crate::W<EGR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<EGR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<EGR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<EGR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22/**Update generation
23
24Value on reset: 0*/
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum UGW_AW {
27    ///1: Re-initializes the timer counter and generates an update of the registers.
28    Trigger = 1,
29}
30impl From<UGW_AW> for bool {
31    #[inline(always)]
32    fn from(variant: UGW_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36///Field `UG` writer - Update generation
37pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, UGW_AW, O>;
38impl<'a, const O: u8> UG_W<'a, O> {
39    ///Re-initializes the timer counter and generates an update of the registers.
40    #[inline(always)]
41    pub fn trigger(self) -> &'a mut W {
42        self.variant(UGW_AW::Trigger)
43    }
44}
45/**Compare/capture1 event
46
47Value on reset: 0*/
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum CC1GW_AW {
50    ///1: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
51    Trigger = 1,
52}
53impl From<CC1GW_AW> for bool {
54    #[inline(always)]
55    fn from(variant: CC1GW_AW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `CC1G` writer - Compare/capture1 event
60pub type CC1G_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, CC1GW_AW, O>;
61impl<'a, const O: u8> CC1G_W<'a, O> {
62    ///If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.
63    #[inline(always)]
64    pub fn trigger(self) -> &'a mut W {
65        self.variant(CC1GW_AW::Trigger)
66    }
67}
68impl W {
69    ///Bit 0 - Update generation
70    #[inline(always)]
71    #[must_use]
72    pub fn ug(&mut self) -> UG_W<0> {
73        UG_W::new(self)
74    }
75    ///Bit 1 - Compare/capture1 event
76    #[inline(always)]
77    #[must_use]
78    pub fn cc1g(&mut self) -> CC1G_W<1> {
79        CC1G_W::new(self)
80    }
81    ///Writes raw bits to the register.
82    #[inline(always)]
83    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
84        self.0.bits(bits);
85        self
86    }
87}
88/**event generation register
89
90This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
91
92For information about available fields see [egr](index.html) module*/
93pub struct EGR_SPEC;
94impl crate::RegisterSpec for EGR_SPEC {
95    type Ux = u32;
96}
97///`write(|w| ..)` method takes [egr::W](W) writer structure
98impl crate::Writable for EGR_SPEC {
99    type Writer = W;
100    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
101    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
102}
103///`reset()` method sets EGR to value 0
104impl crate::Resettable for EGR_SPEC {
105    const RESET_VALUE: Self::Ux = 0;
106}
py32f0/py32f030/tim14/egr.rs

py32f0/py32f030/tim14/
egr.rs
