py32f0/py32f030/tim14/
ccmr1_input.rs

1///Register `CCMR1_Input` reader
2pub struct R(crate::R<CCMR1_INPUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCMR1_INPUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCMR1_INPUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCMR1_INPUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CCMR1_Input` writer
17pub struct W(crate::W<CCMR1_INPUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCMR1_INPUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCMR1_INPUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCMR1_INPUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CC1S` reader - Capture/Compare 1 selection
38pub type CC1S_R = crate::FieldReader<u8, CC1S_A>;
39/**Capture/Compare 1 selection
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u8)]
44pub enum CC1S_A {
45    ///1: CC1 channel is configured as input, IC1 is mapped on TI1
46    Ti1 = 1,
47    ///2: CC1 channel is configured as input, IC1 is mapped on TI2
48    Ti2 = 2,
49    ///3: CC1 channel is configured as input, IC1 is mapped on TRC
50    Trc = 3,
51}
52impl From<CC1S_A> for u8 {
53    #[inline(always)]
54    fn from(variant: CC1S_A) -> Self {
55        variant as _
56    }
57}
58impl CC1S_R {
59    ///Get enumerated values variant
60    #[inline(always)]
61    pub fn variant(&self) -> Option<CC1S_A> {
62        match self.bits {
63            1 => Some(CC1S_A::Ti1),
64            2 => Some(CC1S_A::Ti2),
65            3 => Some(CC1S_A::Trc),
66            _ => None,
67        }
68    }
69    ///Checks if the value of the field is `Ti1`
70    #[inline(always)]
71    pub fn is_ti1(&self) -> bool {
72        *self == CC1S_A::Ti1
73    }
74    ///Checks if the value of the field is `Ti2`
75    #[inline(always)]
76    pub fn is_ti2(&self) -> bool {
77        *self == CC1S_A::Ti2
78    }
79    ///Checks if the value of the field is `Trc`
80    #[inline(always)]
81    pub fn is_trc(&self) -> bool {
82        *self == CC1S_A::Trc
83    }
84}
85///Field `CC1S` writer - Capture/Compare 1 selection
86pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, CC1S_A, 2, O>;
87impl<'a, const O: u8> CC1S_W<'a, O> {
88    ///CC1 channel is configured as input, IC1 is mapped on TI1
89    #[inline(always)]
90    pub fn ti1(self) -> &'a mut W {
91        self.variant(CC1S_A::Ti1)
92    }
93    ///CC1 channel is configured as input, IC1 is mapped on TI2
94    #[inline(always)]
95    pub fn ti2(self) -> &'a mut W {
96        self.variant(CC1S_A::Ti2)
97    }
98    ///CC1 channel is configured as input, IC1 is mapped on TRC
99    #[inline(always)]
100    pub fn trc(self) -> &'a mut W {
101        self.variant(CC1S_A::Trc)
102    }
103}
104///Field `IC1PSC` reader - Input capture 1 prescaler
105pub type IC1PSC_R = crate::FieldReader<u8, u8>;
106///Field `IC1PSC` writer - Input capture 1 prescaler
107pub type IC1PSC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_INPUT_SPEC, u8, u8, 2, O>;
108///Field `IC1F` reader - Input capture 1 filter
109pub type IC1F_R = crate::FieldReader<u8, IC1F_A>;
110/**Input capture 1 filter
111
112Value on reset: 0*/
113#[derive(Clone, Copy, Debug, PartialEq, Eq)]
114#[repr(u8)]
115pub enum IC1F_A {
116    ///0: No filter, sampling is done at fDTS
117    NoFilter = 0,
118    ///1: fSAMPLING=fCK_INT, N=2
119    FckIntN2 = 1,
120    ///2: fSAMPLING=fCK_INT, N=4
121    FckIntN4 = 2,
122    ///3: fSAMPLING=fCK_INT, N=8
123    FckIntN8 = 3,
124    ///4: fSAMPLING=fDTS/2, N=6
125    FdtsDiv2N6 = 4,
126    ///5: fSAMPLING=fDTS/2, N=8
127    FdtsDiv2N8 = 5,
128    ///6: fSAMPLING=fDTS/4, N=6
129    FdtsDiv4N6 = 6,
130    ///7: fSAMPLING=fDTS/4, N=8
131    FdtsDiv4N8 = 7,
132    ///8: fSAMPLING=fDTS/8, N=6
133    FdtsDiv8N6 = 8,
134    ///9: fSAMPLING=fDTS/8, N=8
135    FdtsDiv8N8 = 9,
136    ///10: fSAMPLING=fDTS/16, N=5
137    FdtsDiv16N5 = 10,
138    ///11: fSAMPLING=fDTS/16, N=6
139    FdtsDiv16N6 = 11,
140    ///12: fSAMPLING=fDTS/16, N=8
141    FdtsDiv16N8 = 12,
142    ///13: fSAMPLING=fDTS/32, N=5
143    FdtsDiv32N5 = 13,
144    ///14: fSAMPLING=fDTS/32, N=6
145    FdtsDiv32N6 = 14,
146    ///15: fSAMPLING=fDTS/32, N=8
147    FdtsDiv32N8 = 15,
148}
149impl From<IC1F_A> for u8 {
150    #[inline(always)]
151    fn from(variant: IC1F_A) -> Self {
152        variant as _
153    }
154}
155impl IC1F_R {
156    ///Get enumerated values variant
157    #[inline(always)]
158    pub fn variant(&self) -> IC1F_A {
159        match self.bits {
160            0 => IC1F_A::NoFilter,
161            1 => IC1F_A::FckIntN2,
162            2 => IC1F_A::FckIntN4,
163            3 => IC1F_A::FckIntN8,
164            4 => IC1F_A::FdtsDiv2N6,
165            5 => IC1F_A::FdtsDiv2N8,
166            6 => IC1F_A::FdtsDiv4N6,
167            7 => IC1F_A::FdtsDiv4N8,
168            8 => IC1F_A::FdtsDiv8N6,
169            9 => IC1F_A::FdtsDiv8N8,
170            10 => IC1F_A::FdtsDiv16N5,
171            11 => IC1F_A::FdtsDiv16N6,
172            12 => IC1F_A::FdtsDiv16N8,
173            13 => IC1F_A::FdtsDiv32N5,
174            14 => IC1F_A::FdtsDiv32N6,
175            15 => IC1F_A::FdtsDiv32N8,
176            _ => unreachable!(),
177        }
178    }
179    ///Checks if the value of the field is `NoFilter`
180    #[inline(always)]
181    pub fn is_no_filter(&self) -> bool {
182        *self == IC1F_A::NoFilter
183    }
184    ///Checks if the value of the field is `FckIntN2`
185    #[inline(always)]
186    pub fn is_fck_int_n2(&self) -> bool {
187        *self == IC1F_A::FckIntN2
188    }
189    ///Checks if the value of the field is `FckIntN4`
190    #[inline(always)]
191    pub fn is_fck_int_n4(&self) -> bool {
192        *self == IC1F_A::FckIntN4
193    }
194    ///Checks if the value of the field is `FckIntN8`
195    #[inline(always)]
196    pub fn is_fck_int_n8(&self) -> bool {
197        *self == IC1F_A::FckIntN8
198    }
199    ///Checks if the value of the field is `FdtsDiv2N6`
200    #[inline(always)]
201    pub fn is_fdts_div2_n6(&self) -> bool {
202        *self == IC1F_A::FdtsDiv2N6
203    }
204    ///Checks if the value of the field is `FdtsDiv2N8`
205    #[inline(always)]
206    pub fn is_fdts_div2_n8(&self) -> bool {
207        *self == IC1F_A::FdtsDiv2N8
208    }
209    ///Checks if the value of the field is `FdtsDiv4N6`
210    #[inline(always)]
211    pub fn is_fdts_div4_n6(&self) -> bool {
212        *self == IC1F_A::FdtsDiv4N6
213    }
214    ///Checks if the value of the field is `FdtsDiv4N8`
215    #[inline(always)]
216    pub fn is_fdts_div4_n8(&self) -> bool {
217        *self == IC1F_A::FdtsDiv4N8
218    }
219    ///Checks if the value of the field is `FdtsDiv8N6`
220    #[inline(always)]
221    pub fn is_fdts_div8_n6(&self) -> bool {
222        *self == IC1F_A::FdtsDiv8N6
223    }
224    ///Checks if the value of the field is `FdtsDiv8N8`
225    #[inline(always)]
226    pub fn is_fdts_div8_n8(&self) -> bool {
227        *self == IC1F_A::FdtsDiv8N8
228    }
229    ///Checks if the value of the field is `FdtsDiv16N5`
230    #[inline(always)]
231    pub fn is_fdts_div16_n5(&self) -> bool {
232        *self == IC1F_A::FdtsDiv16N5
233    }
234    ///Checks if the value of the field is `FdtsDiv16N6`
235    #[inline(always)]
236    pub fn is_fdts_div16_n6(&self) -> bool {
237        *self == IC1F_A::FdtsDiv16N6
238    }
239    ///Checks if the value of the field is `FdtsDiv16N8`
240    #[inline(always)]
241    pub fn is_fdts_div16_n8(&self) -> bool {
242        *self == IC1F_A::FdtsDiv16N8
243    }
244    ///Checks if the value of the field is `FdtsDiv32N5`
245    #[inline(always)]
246    pub fn is_fdts_div32_n5(&self) -> bool {
247        *self == IC1F_A::FdtsDiv32N5
248    }
249    ///Checks if the value of the field is `FdtsDiv32N6`
250    #[inline(always)]
251    pub fn is_fdts_div32_n6(&self) -> bool {
252        *self == IC1F_A::FdtsDiv32N6
253    }
254    ///Checks if the value of the field is `FdtsDiv32N8`
255    #[inline(always)]
256    pub fn is_fdts_div32_n8(&self) -> bool {
257        *self == IC1F_A::FdtsDiv32N8
258    }
259}
260///Field `IC1F` writer - Input capture 1 filter
261pub type IC1F_W<'a, const O: u8> =
262    crate::FieldWriterSafe<'a, u32, CCMR1_INPUT_SPEC, u8, IC1F_A, 4, O>;
263impl<'a, const O: u8> IC1F_W<'a, O> {
264    ///No filter, sampling is done at fDTS
265    #[inline(always)]
266    pub fn no_filter(self) -> &'a mut W {
267        self.variant(IC1F_A::NoFilter)
268    }
269    ///fSAMPLING=fCK_INT, N=2
270    #[inline(always)]
271    pub fn fck_int_n2(self) -> &'a mut W {
272        self.variant(IC1F_A::FckIntN2)
273    }
274    ///fSAMPLING=fCK_INT, N=4
275    #[inline(always)]
276    pub fn fck_int_n4(self) -> &'a mut W {
277        self.variant(IC1F_A::FckIntN4)
278    }
279    ///fSAMPLING=fCK_INT, N=8
280    #[inline(always)]
281    pub fn fck_int_n8(self) -> &'a mut W {
282        self.variant(IC1F_A::FckIntN8)
283    }
284    ///fSAMPLING=fDTS/2, N=6
285    #[inline(always)]
286    pub fn fdts_div2_n6(self) -> &'a mut W {
287        self.variant(IC1F_A::FdtsDiv2N6)
288    }
289    ///fSAMPLING=fDTS/2, N=8
290    #[inline(always)]
291    pub fn fdts_div2_n8(self) -> &'a mut W {
292        self.variant(IC1F_A::FdtsDiv2N8)
293    }
294    ///fSAMPLING=fDTS/4, N=6
295    #[inline(always)]
296    pub fn fdts_div4_n6(self) -> &'a mut W {
297        self.variant(IC1F_A::FdtsDiv4N6)
298    }
299    ///fSAMPLING=fDTS/4, N=8
300    #[inline(always)]
301    pub fn fdts_div4_n8(self) -> &'a mut W {
302        self.variant(IC1F_A::FdtsDiv4N8)
303    }
304    ///fSAMPLING=fDTS/8, N=6
305    #[inline(always)]
306    pub fn fdts_div8_n6(self) -> &'a mut W {
307        self.variant(IC1F_A::FdtsDiv8N6)
308    }
309    ///fSAMPLING=fDTS/8, N=8
310    #[inline(always)]
311    pub fn fdts_div8_n8(self) -> &'a mut W {
312        self.variant(IC1F_A::FdtsDiv8N8)
313    }
314    ///fSAMPLING=fDTS/16, N=5
315    #[inline(always)]
316    pub fn fdts_div16_n5(self) -> &'a mut W {
317        self.variant(IC1F_A::FdtsDiv16N5)
318    }
319    ///fSAMPLING=fDTS/16, N=6
320    #[inline(always)]
321    pub fn fdts_div16_n6(self) -> &'a mut W {
322        self.variant(IC1F_A::FdtsDiv16N6)
323    }
324    ///fSAMPLING=fDTS/16, N=8
325    #[inline(always)]
326    pub fn fdts_div16_n8(self) -> &'a mut W {
327        self.variant(IC1F_A::FdtsDiv16N8)
328    }
329    ///fSAMPLING=fDTS/32, N=5
330    #[inline(always)]
331    pub fn fdts_div32_n5(self) -> &'a mut W {
332        self.variant(IC1F_A::FdtsDiv32N5)
333    }
334    ///fSAMPLING=fDTS/32, N=6
335    #[inline(always)]
336    pub fn fdts_div32_n6(self) -> &'a mut W {
337        self.variant(IC1F_A::FdtsDiv32N6)
338    }
339    ///fSAMPLING=fDTS/32, N=8
340    #[inline(always)]
341    pub fn fdts_div32_n8(self) -> &'a mut W {
342        self.variant(IC1F_A::FdtsDiv32N8)
343    }
344}
345impl R {
346    ///Bits 0:1 - Capture/Compare 1 selection
347    #[inline(always)]
348    pub fn cc1s(&self) -> CC1S_R {
349        CC1S_R::new((self.bits & 3) as u8)
350    }
351    ///Bits 2:3 - Input capture 1 prescaler
352    #[inline(always)]
353    pub fn ic1psc(&self) -> IC1PSC_R {
354        IC1PSC_R::new(((self.bits >> 2) & 3) as u8)
355    }
356    ///Bits 4:7 - Input capture 1 filter
357    #[inline(always)]
358    pub fn ic1f(&self) -> IC1F_R {
359        IC1F_R::new(((self.bits >> 4) & 0x0f) as u8)
360    }
361}
362impl W {
363    ///Bits 0:1 - Capture/Compare 1 selection
364    #[inline(always)]
365    #[must_use]
366    pub fn cc1s(&mut self) -> CC1S_W<0> {
367        CC1S_W::new(self)
368    }
369    ///Bits 2:3 - Input capture 1 prescaler
370    #[inline(always)]
371    #[must_use]
372    pub fn ic1psc(&mut self) -> IC1PSC_W<2> {
373        IC1PSC_W::new(self)
374    }
375    ///Bits 4:7 - Input capture 1 filter
376    #[inline(always)]
377    #[must_use]
378    pub fn ic1f(&mut self) -> IC1F_W<4> {
379        IC1F_W::new(self)
380    }
381    ///Writes raw bits to the register.
382    #[inline(always)]
383    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
384        self.0.bits(bits);
385        self
386    }
387}
388/**capture/compare mode register 1 (input mode)
389
390This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
391
392For information about available fields see [ccmr1_input](index.html) module*/
393pub struct CCMR1_INPUT_SPEC;
394impl crate::RegisterSpec for CCMR1_INPUT_SPEC {
395    type Ux = u32;
396}
397///`read()` method returns [ccmr1_input::R](R) reader structure
398impl crate::Readable for CCMR1_INPUT_SPEC {
399    type Reader = R;
400}
401///`write(|w| ..)` method takes [ccmr1_input::W](W) writer structure
402impl crate::Writable for CCMR1_INPUT_SPEC {
403    type Writer = W;
404    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
405    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
406}
407///`reset()` method sets CCMR1_Input to value 0
408impl crate::Resettable for CCMR1_INPUT_SPEC {
409    const RESET_VALUE: Self::Ux = 0;
410}
py32f0/py32f030/tim14/ccmr1_input.rs

py32f0/py32f030/tim14/
ccmr1_input.rs
