py32f0/py32f030/rcc/
ccipr.rs

1///Register `CCIPR` reader
2pub struct R(crate::R<CCIPR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCIPR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCIPR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCIPR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CCIPR` writer
17pub struct W(crate::W<CCIPR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCIPR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCIPR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCIPR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `PVDSEL` reader - PVD detect clock source selection
38pub type PVDSEL_R = crate::BitReader<bool>;
39///Field `PVDSEL` writer - PVD detect clock source selection
40pub type PVDSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCIPR_SPEC, bool, O>;
41///Field `COMP1SEL` reader - COMP1 clock source selection
42pub type COMP1SEL_R = crate::BitReader<COMP1SEL_A>;
43/**COMP1 clock source selection
44
45Value on reset: 0*/
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum COMP1SEL_A {
48    ///0: APB clock selected as Timer clock
49    Pclk = 0,
50    ///1: LSC clock (LSI or LSE selected by LSCOSEL) selected as Timer clock
51    Lsc = 1,
52}
53impl From<COMP1SEL_A> for bool {
54    #[inline(always)]
55    fn from(variant: COMP1SEL_A) -> Self {
56        variant as u8 != 0
57    }
58}
59impl COMP1SEL_R {
60    ///Get enumerated values variant
61    #[inline(always)]
62    pub fn variant(&self) -> COMP1SEL_A {
63        match self.bits {
64            false => COMP1SEL_A::Pclk,
65            true => COMP1SEL_A::Lsc,
66        }
67    }
68    ///Checks if the value of the field is `Pclk`
69    #[inline(always)]
70    pub fn is_pclk(&self) -> bool {
71        *self == COMP1SEL_A::Pclk
72    }
73    ///Checks if the value of the field is `Lsc`
74    #[inline(always)]
75    pub fn is_lsc(&self) -> bool {
76        *self == COMP1SEL_A::Lsc
77    }
78}
79///Field `COMP1SEL` writer - COMP1 clock source selection
80pub type COMP1SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCIPR_SPEC, COMP1SEL_A, O>;
81impl<'a, const O: u8> COMP1SEL_W<'a, O> {
82    ///APB clock selected as Timer clock
83    #[inline(always)]
84    pub fn pclk(self) -> &'a mut W {
85        self.variant(COMP1SEL_A::Pclk)
86    }
87    ///LSC clock (LSI or LSE selected by LSCOSEL) selected as Timer clock
88    #[inline(always)]
89    pub fn lsc(self) -> &'a mut W {
90        self.variant(COMP1SEL_A::Lsc)
91    }
92}
93///Field `COMP2SEL` reader - COMP2 clock source selection
94pub use COMP1SEL_R as COMP2SEL_R;
95///Field `COMP2SEL` writer - COMP2 clock source selection
96pub use COMP1SEL_W as COMP2SEL_W;
97///Field `LPTIM1SEL` reader - LPTIM1 clock source selection
98pub type LPTIM1SEL_R = crate::FieldReader<u8, LPTIM1SEL_A>;
99/**LPTIM1 clock source selection
100
101Value on reset: 0*/
102#[derive(Clone, Copy, Debug, PartialEq, Eq)]
103#[repr(u8)]
104pub enum LPTIM1SEL_A {
105    ///0: APB clock selected as Timer clock
106    Pclk = 0,
107    ///1: LSI clock selected as Timer clock
108    Lsi = 1,
109    ///3: LSE clock selected as Timer clock
110    Lse = 3,
111}
112impl From<LPTIM1SEL_A> for u8 {
113    #[inline(always)]
114    fn from(variant: LPTIM1SEL_A) -> Self {
115        variant as _
116    }
117}
118impl LPTIM1SEL_R {
119    ///Get enumerated values variant
120    #[inline(always)]
121    pub fn variant(&self) -> LPTIM1SEL_A {
122        match self.bits {
123            0 => LPTIM1SEL_A::Pclk,
124            1 => LPTIM1SEL_A::Lsi,
125            3 => LPTIM1SEL_A::Lse,
126            _ => unreachable!(),
127        }
128    }
129    ///Checks if the value of the field is `Pclk`
130    #[inline(always)]
131    pub fn is_pclk(&self) -> bool {
132        *self == LPTIM1SEL_A::Pclk
133    }
134    ///Checks if the value of the field is `Lsi`
135    #[inline(always)]
136    pub fn is_lsi(&self) -> bool {
137        *self == LPTIM1SEL_A::Lsi
138    }
139    ///Checks if the value of the field is `Lse`
140    #[inline(always)]
141    pub fn is_lse(&self) -> bool {
142        *self == LPTIM1SEL_A::Lse
143    }
144}
145///Field `LPTIM1SEL` writer - LPTIM1 clock source selection
146pub type LPTIM1SEL_W<'a, const O: u8> =
147    crate::FieldWriter<'a, u32, CCIPR_SPEC, u8, LPTIM1SEL_A, 2, O>;
148impl<'a, const O: u8> LPTIM1SEL_W<'a, O> {
149    ///APB clock selected as Timer clock
150    #[inline(always)]
151    pub fn pclk(self) -> &'a mut W {
152        self.variant(LPTIM1SEL_A::Pclk)
153    }
154    ///LSI clock selected as Timer clock
155    #[inline(always)]
156    pub fn lsi(self) -> &'a mut W {
157        self.variant(LPTIM1SEL_A::Lsi)
158    }
159    ///LSE clock selected as Timer clock
160    #[inline(always)]
161    pub fn lse(self) -> &'a mut W {
162        self.variant(LPTIM1SEL_A::Lse)
163    }
164}
165impl R {
166    ///Bit 7 - PVD detect clock source selection
167    #[inline(always)]
168    pub fn pvdsel(&self) -> PVDSEL_R {
169        PVDSEL_R::new(((self.bits >> 7) & 1) != 0)
170    }
171    ///Bit 8 - COMP1 clock source selection
172    #[inline(always)]
173    pub fn comp1sel(&self) -> COMP1SEL_R {
174        COMP1SEL_R::new(((self.bits >> 8) & 1) != 0)
175    }
176    ///Bit 9 - COMP2 clock source selection
177    #[inline(always)]
178    pub fn comp2sel(&self) -> COMP2SEL_R {
179        COMP2SEL_R::new(((self.bits >> 9) & 1) != 0)
180    }
181    ///Bits 18:19 - LPTIM1 clock source selection
182    #[inline(always)]
183    pub fn lptim1sel(&self) -> LPTIM1SEL_R {
184        LPTIM1SEL_R::new(((self.bits >> 18) & 3) as u8)
185    }
186}
187impl W {
188    ///Bit 7 - PVD detect clock source selection
189    #[inline(always)]
190    #[must_use]
191    pub fn pvdsel(&mut self) -> PVDSEL_W<7> {
192        PVDSEL_W::new(self)
193    }
194    ///Bit 8 - COMP1 clock source selection
195    #[inline(always)]
196    #[must_use]
197    pub fn comp1sel(&mut self) -> COMP1SEL_W<8> {
198        COMP1SEL_W::new(self)
199    }
200    ///Bit 9 - COMP2 clock source selection
201    #[inline(always)]
202    #[must_use]
203    pub fn comp2sel(&mut self) -> COMP2SEL_W<9> {
204        COMP2SEL_W::new(self)
205    }
206    ///Bits 18:19 - LPTIM1 clock source selection
207    #[inline(always)]
208    #[must_use]
209    pub fn lptim1sel(&mut self) -> LPTIM1SEL_W<18> {
210        LPTIM1SEL_W::new(self)
211    }
212    ///Writes raw bits to the register.
213    #[inline(always)]
214    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
215        self.0.bits(bits);
216        self
217    }
218}
219/**Peripherals independent clock configuration register
220
221This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
222
223For information about available fields see [ccipr](index.html) module*/
224pub struct CCIPR_SPEC;
225impl crate::RegisterSpec for CCIPR_SPEC {
226    type Ux = u32;
227}
228///`read()` method returns [ccipr::R](R) reader structure
229impl crate::Readable for CCIPR_SPEC {
230    type Reader = R;
231}
232///`write(|w| ..)` method takes [ccipr::W](W) writer structure
233impl crate::Writable for CCIPR_SPEC {
234    type Writer = W;
235    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
236    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
237}
238///`reset()` method sets CCIPR to value 0
239impl crate::Resettable for CCIPR_SPEC {
240    const RESET_VALUE: Self::Ux = 0;
241}
py32f0/py32f030/rcc/ccipr.rs

py32f0/py32f030/rcc/
ccipr.rs
