py32f0/py32f030/dma/
isr.rs

1///Register `ISR` reader
2pub struct R(crate::R<ISR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ISR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ISR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ISR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Field `GIF[1-3]` reader - Channel %s Global interrupt flag
17pub type GIF_R = crate::BitReader<GIF1_A>;
18/**Channel %s Global interrupt flag
19
20Value on reset: 0*/
21#[derive(Clone, Copy, Debug, PartialEq, Eq)]
22pub enum GIF1_A {
23    ///0: No transfer error, half event, complete event
24    NoEvent = 0,
25    ///1: A transfer error, half event or complete event has occured
26    Event = 1,
27}
28impl From<GIF1_A> for bool {
29    #[inline(always)]
30    fn from(variant: GIF1_A) -> Self {
31        variant as u8 != 0
32    }
33}
34impl GIF_R {
35    ///Get enumerated values variant
36    #[inline(always)]
37    pub fn variant(&self) -> GIF1_A {
38        match self.bits {
39            false => GIF1_A::NoEvent,
40            true => GIF1_A::Event,
41        }
42    }
43    ///Checks if the value of the field is `NoEvent`
44    #[inline(always)]
45    pub fn is_no_event(&self) -> bool {
46        *self == GIF1_A::NoEvent
47    }
48    ///Checks if the value of the field is `Event`
49    #[inline(always)]
50    pub fn is_event(&self) -> bool {
51        *self == GIF1_A::Event
52    }
53}
54///Field `TCIF[1-3]` reader - Channel %s Transfer Complete flag
55pub type TCIF_R = crate::BitReader<TCIF1_A>;
56/**Channel %s Transfer Complete flag
57
58Value on reset: 0*/
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum TCIF1_A {
61    ///0: No transfer complete event
62    NotComplete = 0,
63    ///1: A transfer complete event has occured
64    Complete = 1,
65}
66impl From<TCIF1_A> for bool {
67    #[inline(always)]
68    fn from(variant: TCIF1_A) -> Self {
69        variant as u8 != 0
70    }
71}
72impl TCIF_R {
73    ///Get enumerated values variant
74    #[inline(always)]
75    pub fn variant(&self) -> TCIF1_A {
76        match self.bits {
77            false => TCIF1_A::NotComplete,
78            true => TCIF1_A::Complete,
79        }
80    }
81    ///Checks if the value of the field is `NotComplete`
82    #[inline(always)]
83    pub fn is_not_complete(&self) -> bool {
84        *self == TCIF1_A::NotComplete
85    }
86    ///Checks if the value of the field is `Complete`
87    #[inline(always)]
88    pub fn is_complete(&self) -> bool {
89        *self == TCIF1_A::Complete
90    }
91}
92///Field `HTIF[1-3]` reader - Channel %s Half Transfer Complete flag
93pub type HTIF_R = crate::BitReader<HTIF1_A>;
94/**Channel %s Half Transfer Complete flag
95
96Value on reset: 0*/
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum HTIF1_A {
99    ///0: No half transfer event
100    NotHalf = 0,
101    ///1: A half transfer event has occured
102    Half = 1,
103}
104impl From<HTIF1_A> for bool {
105    #[inline(always)]
106    fn from(variant: HTIF1_A) -> Self {
107        variant as u8 != 0
108    }
109}
110impl HTIF_R {
111    ///Get enumerated values variant
112    #[inline(always)]
113    pub fn variant(&self) -> HTIF1_A {
114        match self.bits {
115            false => HTIF1_A::NotHalf,
116            true => HTIF1_A::Half,
117        }
118    }
119    ///Checks if the value of the field is `NotHalf`
120    #[inline(always)]
121    pub fn is_not_half(&self) -> bool {
122        *self == HTIF1_A::NotHalf
123    }
124    ///Checks if the value of the field is `Half`
125    #[inline(always)]
126    pub fn is_half(&self) -> bool {
127        *self == HTIF1_A::Half
128    }
129}
130///Field `TEIF[1-3]` reader - Channel %s Transfer Error flag
131pub type TEIF_R = crate::BitReader<TEIF1_A>;
132/**Channel %s Transfer Error flag
133
134Value on reset: 0*/
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum TEIF1_A {
137    ///0: No transfer error
138    NoError = 0,
139    ///1: A transfer error has occured
140    Error = 1,
141}
142impl From<TEIF1_A> for bool {
143    #[inline(always)]
144    fn from(variant: TEIF1_A) -> Self {
145        variant as u8 != 0
146    }
147}
148impl TEIF_R {
149    ///Get enumerated values variant
150    #[inline(always)]
151    pub fn variant(&self) -> TEIF1_A {
152        match self.bits {
153            false => TEIF1_A::NoError,
154            true => TEIF1_A::Error,
155        }
156    }
157    ///Checks if the value of the field is `NoError`
158    #[inline(always)]
159    pub fn is_no_error(&self) -> bool {
160        *self == TEIF1_A::NoError
161    }
162    ///Checks if the value of the field is `Error`
163    #[inline(always)]
164    pub fn is_error(&self) -> bool {
165        *self == TEIF1_A::Error
166    }
167}
168impl R {
169    /**Channel [1-3]
170    Global interrupt flag*/
171    #[inline(always)]
172    pub unsafe fn gif(&self, n: u8) -> GIF_R {
173        GIF_R::new(((self.bits >> ((n - 1) * 4)) & 1) != 0)
174    }
175    ///Bit 0 - Channel 1 Global interrupt flag
176    #[inline(always)]
177    pub fn gif1(&self) -> GIF_R {
178        GIF_R::new((self.bits & 1) != 0)
179    }
180    ///Bit 4 - Channel 2 Global interrupt flag
181    #[inline(always)]
182    pub fn gif2(&self) -> GIF_R {
183        GIF_R::new(((self.bits >> 4) & 1) != 0)
184    }
185    ///Bit 8 - Channel 3 Global interrupt flag
186    #[inline(always)]
187    pub fn gif3(&self) -> GIF_R {
188        GIF_R::new(((self.bits >> 8) & 1) != 0)
189    }
190    /**Channel [1-3]
191    Transfer Complete flag*/
192    #[inline(always)]
193    pub unsafe fn tcif(&self, n: u8) -> TCIF_R {
194        TCIF_R::new(((self.bits >> ((n - 1) * 4 + 1)) & 1) != 0)
195    }
196    ///Bit 1 - Channel 1 Transfer Complete flag
197    #[inline(always)]
198    pub fn tcif1(&self) -> TCIF_R {
199        TCIF_R::new(((self.bits >> 1) & 1) != 0)
200    }
201    ///Bit 5 - Channel 2 Transfer Complete flag
202    #[inline(always)]
203    pub fn tcif2(&self) -> TCIF_R {
204        TCIF_R::new(((self.bits >> 5) & 1) != 0)
205    }
206    ///Bit 9 - Channel 3 Transfer Complete flag
207    #[inline(always)]
208    pub fn tcif3(&self) -> TCIF_R {
209        TCIF_R::new(((self.bits >> 9) & 1) != 0)
210    }
211    /**Channel [1-3]
212    Half Transfer Complete flag*/
213    #[inline(always)]
214    pub unsafe fn htif(&self, n: u8) -> HTIF_R {
215        HTIF_R::new(((self.bits >> ((n - 1) * 4 + 2)) & 1) != 0)
216    }
217    ///Bit 2 - Channel 1 Half Transfer Complete flag
218    #[inline(always)]
219    pub fn htif1(&self) -> HTIF_R {
220        HTIF_R::new(((self.bits >> 2) & 1) != 0)
221    }
222    ///Bit 6 - Channel 2 Half Transfer Complete flag
223    #[inline(always)]
224    pub fn htif2(&self) -> HTIF_R {
225        HTIF_R::new(((self.bits >> 6) & 1) != 0)
226    }
227    ///Bit 10 - Channel 3 Half Transfer Complete flag
228    #[inline(always)]
229    pub fn htif3(&self) -> HTIF_R {
230        HTIF_R::new(((self.bits >> 10) & 1) != 0)
231    }
232    /**Channel [1-3]
233    Transfer Error flag*/
234    #[inline(always)]
235    pub unsafe fn teif(&self, n: u8) -> TEIF_R {
236        TEIF_R::new(((self.bits >> ((n - 1) * 4 + 3)) & 1) != 0)
237    }
238    ///Bit 3 - Channel 1 Transfer Error flag
239    #[inline(always)]
240    pub fn teif1(&self) -> TEIF_R {
241        TEIF_R::new(((self.bits >> 3) & 1) != 0)
242    }
243    ///Bit 7 - Channel 2 Transfer Error flag
244    #[inline(always)]
245    pub fn teif2(&self) -> TEIF_R {
246        TEIF_R::new(((self.bits >> 7) & 1) != 0)
247    }
248    ///Bit 11 - Channel 3 Transfer Error flag
249    #[inline(always)]
250    pub fn teif3(&self) -> TEIF_R {
251        TEIF_R::new(((self.bits >> 11) & 1) != 0)
252    }
253}
254/**DMA interrupt status register (DMA_ISR)
255
256This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
257
258For information about available fields see [isr](index.html) module*/
259pub struct ISR_SPEC;
260impl crate::RegisterSpec for ISR_SPEC {
261    type Ux = u32;
262}
263///`read()` method returns [isr::R](R) reader structure
264impl crate::Readable for ISR_SPEC {
265    type Reader = R;
266}
267///`reset()` method sets ISR to value 0
268impl crate::Resettable for ISR_SPEC {
269    const RESET_VALUE: Self::Ux = 0;
270}
py32f0/py32f030/dma/isr.rs

py32f0/py32f030/dma/
isr.rs
