py32f0/py32f030/adc/
cr.rs

1///Register `CR` reader
2pub struct R(crate::R<CR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR` writer
17pub struct W(crate::W<CR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `ADEN` reader - ADC enable
38pub type ADEN_R = crate::BitReader<ADENR_A>;
39/**ADC enable
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum ADENR_A {
44    ///0: ADC disabled
45    Disabled = 0,
46    ///1: ADC enabled
47    Enabled = 1,
48}
49impl From<ADENR_A> for bool {
50    #[inline(always)]
51    fn from(variant: ADENR_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl ADEN_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> ADENR_A {
59        match self.bits {
60            false => ADENR_A::Disabled,
61            true => ADENR_A::Enabled,
62        }
63    }
64    ///Checks if the value of the field is `Disabled`
65    #[inline(always)]
66    pub fn is_disabled(&self) -> bool {
67        *self == ADENR_A::Disabled
68    }
69    ///Checks if the value of the field is `Enabled`
70    #[inline(always)]
71    pub fn is_enabled(&self) -> bool {
72        *self == ADENR_A::Enabled
73    }
74}
75/**ADC enable
76
77Value on reset: 0*/
78#[derive(Clone, Copy, Debug, PartialEq, Eq)]
79pub enum ADENW_AW {
80    ///1: Enable the ADC
81    Enabled = 1,
82}
83impl From<ADENW_AW> for bool {
84    #[inline(always)]
85    fn from(variant: ADENW_AW) -> Self {
86        variant as u8 != 0
87    }
88}
89///Field `ADEN` writer - ADC enable
90pub type ADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, ADENW_AW, O>;
91impl<'a, const O: u8> ADEN_W<'a, O> {
92    ///Enable the ADC
93    #[inline(always)]
94    pub fn enabled(self) -> &'a mut W {
95        self.variant(ADENW_AW::Enabled)
96    }
97}
98///Field `ADDIS` reader - ADC disabling
99pub type ADDIS_R = crate::BitReader<ADDISR_A>;
100/**ADC disabling
101
102Value on reset: 0*/
103#[derive(Clone, Copy, Debug, PartialEq, Eq)]
104pub enum ADDISR_A {
105    ///0: No disable command active
106    NotDisabling = 0,
107    ///1: ADC disabling
108    Disabling = 1,
109}
110impl From<ADDISR_A> for bool {
111    #[inline(always)]
112    fn from(variant: ADDISR_A) -> Self {
113        variant as u8 != 0
114    }
115}
116impl ADDIS_R {
117    ///Get enumerated values variant
118    #[inline(always)]
119    pub fn variant(&self) -> ADDISR_A {
120        match self.bits {
121            false => ADDISR_A::NotDisabling,
122            true => ADDISR_A::Disabling,
123        }
124    }
125    ///Checks if the value of the field is `NotDisabling`
126    #[inline(always)]
127    pub fn is_not_disabling(&self) -> bool {
128        *self == ADDISR_A::NotDisabling
129    }
130    ///Checks if the value of the field is `Disabling`
131    #[inline(always)]
132    pub fn is_disabling(&self) -> bool {
133        *self == ADDISR_A::Disabling
134    }
135}
136/**ADC disabling
137
138Value on reset: 0*/
139#[derive(Clone, Copy, Debug, PartialEq, Eq)]
140pub enum ADDISW_AW {
141    ///1: Disable the ADC
142    Disable = 1,
143}
144impl From<ADDISW_AW> for bool {
145    #[inline(always)]
146    fn from(variant: ADDISW_AW) -> Self {
147        variant as u8 != 0
148    }
149}
150///Field `ADDIS` writer - ADC disabling
151pub type ADDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, ADDISW_AW, O>;
152impl<'a, const O: u8> ADDIS_W<'a, O> {
153    ///Disable the ADC
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut W {
156        self.variant(ADDISW_AW::Disable)
157    }
158}
159///Field `ADSTART` reader - ADC group regular conversion start
160pub type ADSTART_R = crate::BitReader<ADSTARTR_A>;
161/**ADC group regular conversion start
162
163Value on reset: 0*/
164#[derive(Clone, Copy, Debug, PartialEq, Eq)]
165pub enum ADSTARTR_A {
166    ///0: No conversion ongoing
167    NotActive = 0,
168    ///1: ADC operating and may be converting
169    Active = 1,
170}
171impl From<ADSTARTR_A> for bool {
172    #[inline(always)]
173    fn from(variant: ADSTARTR_A) -> Self {
174        variant as u8 != 0
175    }
176}
177impl ADSTART_R {
178    ///Get enumerated values variant
179    #[inline(always)]
180    pub fn variant(&self) -> ADSTARTR_A {
181        match self.bits {
182            false => ADSTARTR_A::NotActive,
183            true => ADSTARTR_A::Active,
184        }
185    }
186    ///Checks if the value of the field is `NotActive`
187    #[inline(always)]
188    pub fn is_not_active(&self) -> bool {
189        *self == ADSTARTR_A::NotActive
190    }
191    ///Checks if the value of the field is `Active`
192    #[inline(always)]
193    pub fn is_active(&self) -> bool {
194        *self == ADSTARTR_A::Active
195    }
196}
197/**ADC group regular conversion start
198
199Value on reset: 0*/
200#[derive(Clone, Copy, Debug, PartialEq, Eq)]
201pub enum ADSTARTW_AW {
202    ///1: Start the ADC conversion (may be delayed for hardware triggers)
203    StartConversion = 1,
204}
205impl From<ADSTARTW_AW> for bool {
206    #[inline(always)]
207    fn from(variant: ADSTARTW_AW) -> Self {
208        variant as u8 != 0
209    }
210}
211///Field `ADSTART` writer - ADC group regular conversion start
212pub type ADSTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, ADSTARTW_AW, O>;
213impl<'a, const O: u8> ADSTART_W<'a, O> {
214    ///Start the ADC conversion (may be delayed for hardware triggers)
215    #[inline(always)]
216    pub fn start_conversion(self) -> &'a mut W {
217        self.variant(ADSTARTW_AW::StartConversion)
218    }
219}
220///Field `ADSTP` reader - ADC group regular conversion stop
221pub type ADSTP_R = crate::BitReader<ADSTPR_A>;
222/**ADC group regular conversion stop
223
224Value on reset: 0*/
225#[derive(Clone, Copy, Debug, PartialEq, Eq)]
226pub enum ADSTPR_A {
227    ///0: No stop command active
228    NotStopping = 0,
229    ///1: ADC stopping conversion
230    Stopping = 1,
231}
232impl From<ADSTPR_A> for bool {
233    #[inline(always)]
234    fn from(variant: ADSTPR_A) -> Self {
235        variant as u8 != 0
236    }
237}
238impl ADSTP_R {
239    ///Get enumerated values variant
240    #[inline(always)]
241    pub fn variant(&self) -> ADSTPR_A {
242        match self.bits {
243            false => ADSTPR_A::NotStopping,
244            true => ADSTPR_A::Stopping,
245        }
246    }
247    ///Checks if the value of the field is `NotStopping`
248    #[inline(always)]
249    pub fn is_not_stopping(&self) -> bool {
250        *self == ADSTPR_A::NotStopping
251    }
252    ///Checks if the value of the field is `Stopping`
253    #[inline(always)]
254    pub fn is_stopping(&self) -> bool {
255        *self == ADSTPR_A::Stopping
256    }
257}
258/**ADC group regular conversion stop
259
260Value on reset: 0*/
261#[derive(Clone, Copy, Debug, PartialEq, Eq)]
262pub enum ADSTPW_AW {
263    ///1: Stop the active conversion
264    StopConversion = 1,
265}
266impl From<ADSTPW_AW> for bool {
267    #[inline(always)]
268    fn from(variant: ADSTPW_AW) -> Self {
269        variant as u8 != 0
270    }
271}
272///Field `ADSTP` writer - ADC group regular conversion stop
273pub type ADSTP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, ADSTPW_AW, O>;
274impl<'a, const O: u8> ADSTP_W<'a, O> {
275    ///Stop the active conversion
276    #[inline(always)]
277    pub fn stop_conversion(self) -> &'a mut W {
278        self.variant(ADSTPW_AW::StopConversion)
279    }
280}
281///Field `ADCAL` reader - ADC group regular conversion calibration
282pub type ADCAL_R = crate::BitReader<ADCALR_A>;
283/**ADC group regular conversion calibration
284
285Value on reset: 0*/
286#[derive(Clone, Copy, Debug, PartialEq, Eq)]
287pub enum ADCALR_A {
288    ///0: ADC calibration either not yet performed or completed
289    NotCalibrating = 0,
290    ///1: ADC calibration in progress
291    Calibrating = 1,
292}
293impl From<ADCALR_A> for bool {
294    #[inline(always)]
295    fn from(variant: ADCALR_A) -> Self {
296        variant as u8 != 0
297    }
298}
299impl ADCAL_R {
300    ///Get enumerated values variant
301    #[inline(always)]
302    pub fn variant(&self) -> ADCALR_A {
303        match self.bits {
304            false => ADCALR_A::NotCalibrating,
305            true => ADCALR_A::Calibrating,
306        }
307    }
308    ///Checks if the value of the field is `NotCalibrating`
309    #[inline(always)]
310    pub fn is_not_calibrating(&self) -> bool {
311        *self == ADCALR_A::NotCalibrating
312    }
313    ///Checks if the value of the field is `Calibrating`
314    #[inline(always)]
315    pub fn is_calibrating(&self) -> bool {
316        *self == ADCALR_A::Calibrating
317    }
318}
319/**ADC group regular conversion calibration
320
321Value on reset: 0*/
322#[derive(Clone, Copy, Debug, PartialEq, Eq)]
323pub enum ADCALW_AW {
324    ///1: Start the ADC calibration sequence
325    StartCalibration = 1,
326}
327impl From<ADCALW_AW> for bool {
328    #[inline(always)]
329    fn from(variant: ADCALW_AW) -> Self {
330        variant as u8 != 0
331    }
332}
333///Field `ADCAL` writer - ADC group regular conversion calibration
334pub type ADCAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, ADCALW_AW, O>;
335impl<'a, const O: u8> ADCAL_W<'a, O> {
336    ///Start the ADC calibration sequence
337    #[inline(always)]
338    pub fn start_calibration(self) -> &'a mut W {
339        self.variant(ADCALW_AW::StartCalibration)
340    }
341}
342impl R {
343    ///Bit 0 - ADC enable
344    #[inline(always)]
345    pub fn aden(&self) -> ADEN_R {
346        ADEN_R::new((self.bits & 1) != 0)
347    }
348    ///Bit 1 - ADC disabling
349    #[inline(always)]
350    pub fn addis(&self) -> ADDIS_R {
351        ADDIS_R::new(((self.bits >> 1) & 1) != 0)
352    }
353    ///Bit 2 - ADC group regular conversion start
354    #[inline(always)]
355    pub fn adstart(&self) -> ADSTART_R {
356        ADSTART_R::new(((self.bits >> 2) & 1) != 0)
357    }
358    ///Bit 4 - ADC group regular conversion stop
359    #[inline(always)]
360    pub fn adstp(&self) -> ADSTP_R {
361        ADSTP_R::new(((self.bits >> 4) & 1) != 0)
362    }
363    ///Bit 31 - ADC group regular conversion calibration
364    #[inline(always)]
365    pub fn adcal(&self) -> ADCAL_R {
366        ADCAL_R::new(((self.bits >> 31) & 1) != 0)
367    }
368}
369impl W {
370    ///Bit 0 - ADC enable
371    #[inline(always)]
372    #[must_use]
373    pub fn aden(&mut self) -> ADEN_W<0> {
374        ADEN_W::new(self)
375    }
376    ///Bit 1 - ADC disabling
377    #[inline(always)]
378    #[must_use]
379    pub fn addis(&mut self) -> ADDIS_W<1> {
380        ADDIS_W::new(self)
381    }
382    ///Bit 2 - ADC group regular conversion start
383    #[inline(always)]
384    #[must_use]
385    pub fn adstart(&mut self) -> ADSTART_W<2> {
386        ADSTART_W::new(self)
387    }
388    ///Bit 4 - ADC group regular conversion stop
389    #[inline(always)]
390    #[must_use]
391    pub fn adstp(&mut self) -> ADSTP_W<4> {
392        ADSTP_W::new(self)
393    }
394    ///Bit 31 - ADC group regular conversion calibration
395    #[inline(always)]
396    #[must_use]
397    pub fn adcal(&mut self) -> ADCAL_W<31> {
398        ADCAL_W::new(self)
399    }
400    ///Writes raw bits to the register.
401    #[inline(always)]
402    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
403        self.0.bits(bits);
404        self
405    }
406}
407/**ADC control register
408
409This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
410
411For information about available fields see [cr](index.html) module*/
412pub struct CR_SPEC;
413impl crate::RegisterSpec for CR_SPEC {
414    type Ux = u32;
415}
416///`read()` method returns [cr::R](R) reader structure
417impl crate::Readable for CR_SPEC {
418    type Reader = R;
419}
420///`write(|w| ..)` method takes [cr::W](W) writer structure
421impl crate::Writable for CR_SPEC {
422    type Writer = W;
423    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
424    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
425}
426///`reset()` method sets CR to value 0
427impl crate::Resettable for CR_SPEC {
428    const RESET_VALUE: Self::Ux = 0;
429}
py32f0/py32f030/adc/cr.rs

py32f0/py32f030/adc/
cr.rs
