py32f0/py32f003/tim3/
cr1.rs

1///Register `CR1` reader
2pub struct R(crate::R<CR1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR1` writer
17pub struct W(crate::W<CR1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CEN` reader - Counter enable
38pub type CEN_R = crate::BitReader<CEN_A>;
39/**Counter enable
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum CEN_A {
44    ///0: Counter disabled
45    Disabled = 0,
46    ///1: Counter enabled
47    Enabled = 1,
48}
49impl From<CEN_A> for bool {
50    #[inline(always)]
51    fn from(variant: CEN_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl CEN_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> CEN_A {
59        match self.bits {
60            false => CEN_A::Disabled,
61            true => CEN_A::Enabled,
62        }
63    }
64    ///Checks if the value of the field is `Disabled`
65    #[inline(always)]
66    pub fn is_disabled(&self) -> bool {
67        *self == CEN_A::Disabled
68    }
69    ///Checks if the value of the field is `Enabled`
70    #[inline(always)]
71    pub fn is_enabled(&self) -> bool {
72        *self == CEN_A::Enabled
73    }
74}
75///Field `CEN` writer - Counter enable
76pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, CEN_A, O>;
77impl<'a, const O: u8> CEN_W<'a, O> {
78    ///Counter disabled
79    #[inline(always)]
80    pub fn disabled(self) -> &'a mut W {
81        self.variant(CEN_A::Disabled)
82    }
83    ///Counter enabled
84    #[inline(always)]
85    pub fn enabled(self) -> &'a mut W {
86        self.variant(CEN_A::Enabled)
87    }
88}
89///Field `UDIS` reader - Update disable
90pub type UDIS_R = crate::BitReader<UDIS_A>;
91/**Update disable
92
93Value on reset: 0*/
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum UDIS_A {
96    ///0: Update event enabled
97    Enabled = 0,
98    ///1: Update event disabled
99    Disabled = 1,
100}
101impl From<UDIS_A> for bool {
102    #[inline(always)]
103    fn from(variant: UDIS_A) -> Self {
104        variant as u8 != 0
105    }
106}
107impl UDIS_R {
108    ///Get enumerated values variant
109    #[inline(always)]
110    pub fn variant(&self) -> UDIS_A {
111        match self.bits {
112            false => UDIS_A::Enabled,
113            true => UDIS_A::Disabled,
114        }
115    }
116    ///Checks if the value of the field is `Enabled`
117    #[inline(always)]
118    pub fn is_enabled(&self) -> bool {
119        *self == UDIS_A::Enabled
120    }
121    ///Checks if the value of the field is `Disabled`
122    #[inline(always)]
123    pub fn is_disabled(&self) -> bool {
124        *self == UDIS_A::Disabled
125    }
126}
127///Field `UDIS` writer - Update disable
128pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, UDIS_A, O>;
129impl<'a, const O: u8> UDIS_W<'a, O> {
130    ///Update event enabled
131    #[inline(always)]
132    pub fn enabled(self) -> &'a mut W {
133        self.variant(UDIS_A::Enabled)
134    }
135    ///Update event disabled
136    #[inline(always)]
137    pub fn disabled(self) -> &'a mut W {
138        self.variant(UDIS_A::Disabled)
139    }
140}
141///Field `URS` reader - Update request source
142pub type URS_R = crate::BitReader<URS_A>;
143/**Update request source
144
145Value on reset: 0*/
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum URS_A {
148    ///0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
149    AnyEvent = 0,
150    ///1: Only counter overflow/underflow generates an update interrupt or DMA request
151    CounterOnly = 1,
152}
153impl From<URS_A> for bool {
154    #[inline(always)]
155    fn from(variant: URS_A) -> Self {
156        variant as u8 != 0
157    }
158}
159impl URS_R {
160    ///Get enumerated values variant
161    #[inline(always)]
162    pub fn variant(&self) -> URS_A {
163        match self.bits {
164            false => URS_A::AnyEvent,
165            true => URS_A::CounterOnly,
166        }
167    }
168    ///Checks if the value of the field is `AnyEvent`
169    #[inline(always)]
170    pub fn is_any_event(&self) -> bool {
171        *self == URS_A::AnyEvent
172    }
173    ///Checks if the value of the field is `CounterOnly`
174    #[inline(always)]
175    pub fn is_counter_only(&self) -> bool {
176        *self == URS_A::CounterOnly
177    }
178}
179///Field `URS` writer - Update request source
180pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, URS_A, O>;
181impl<'a, const O: u8> URS_W<'a, O> {
182    ///Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
183    #[inline(always)]
184    pub fn any_event(self) -> &'a mut W {
185        self.variant(URS_A::AnyEvent)
186    }
187    ///Only counter overflow/underflow generates an update interrupt or DMA request
188    #[inline(always)]
189    pub fn counter_only(self) -> &'a mut W {
190        self.variant(URS_A::CounterOnly)
191    }
192}
193///Field `OPM` reader - One-pulse mode
194pub type OPM_R = crate::BitReader<OPM_A>;
195/**One-pulse mode
196
197Value on reset: 0*/
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199pub enum OPM_A {
200    ///0: Counter is not stopped at update event
201    Disabled = 0,
202    ///1: Counter stops counting at the next update event (clearing the CEN bit)
203    Enabled = 1,
204}
205impl From<OPM_A> for bool {
206    #[inline(always)]
207    fn from(variant: OPM_A) -> Self {
208        variant as u8 != 0
209    }
210}
211impl OPM_R {
212    ///Get enumerated values variant
213    #[inline(always)]
214    pub fn variant(&self) -> OPM_A {
215        match self.bits {
216            false => OPM_A::Disabled,
217            true => OPM_A::Enabled,
218        }
219    }
220    ///Checks if the value of the field is `Disabled`
221    #[inline(always)]
222    pub fn is_disabled(&self) -> bool {
223        *self == OPM_A::Disabled
224    }
225    ///Checks if the value of the field is `Enabled`
226    #[inline(always)]
227    pub fn is_enabled(&self) -> bool {
228        *self == OPM_A::Enabled
229    }
230}
231///Field `OPM` writer - One-pulse mode
232pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, OPM_A, O>;
233impl<'a, const O: u8> OPM_W<'a, O> {
234    ///Counter is not stopped at update event
235    #[inline(always)]
236    pub fn disabled(self) -> &'a mut W {
237        self.variant(OPM_A::Disabled)
238    }
239    ///Counter stops counting at the next update event (clearing the CEN bit)
240    #[inline(always)]
241    pub fn enabled(self) -> &'a mut W {
242        self.variant(OPM_A::Enabled)
243    }
244}
245///Field `DIR` reader - Direction
246pub type DIR_R = crate::BitReader<DIR_A>;
247/**Direction
248
249Value on reset: 0*/
250#[derive(Clone, Copy, Debug, PartialEq, Eq)]
251pub enum DIR_A {
252    ///0: Counter used as upcounter
253    Up = 0,
254    ///1: Counter used as downcounter
255    Down = 1,
256}
257impl From<DIR_A> for bool {
258    #[inline(always)]
259    fn from(variant: DIR_A) -> Self {
260        variant as u8 != 0
261    }
262}
263impl DIR_R {
264    ///Get enumerated values variant
265    #[inline(always)]
266    pub fn variant(&self) -> DIR_A {
267        match self.bits {
268            false => DIR_A::Up,
269            true => DIR_A::Down,
270        }
271    }
272    ///Checks if the value of the field is `Up`
273    #[inline(always)]
274    pub fn is_up(&self) -> bool {
275        *self == DIR_A::Up
276    }
277    ///Checks if the value of the field is `Down`
278    #[inline(always)]
279    pub fn is_down(&self) -> bool {
280        *self == DIR_A::Down
281    }
282}
283///Field `DIR` writer - Direction
284pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, DIR_A, O>;
285impl<'a, const O: u8> DIR_W<'a, O> {
286    ///Counter used as upcounter
287    #[inline(always)]
288    pub fn up(self) -> &'a mut W {
289        self.variant(DIR_A::Up)
290    }
291    ///Counter used as downcounter
292    #[inline(always)]
293    pub fn down(self) -> &'a mut W {
294        self.variant(DIR_A::Down)
295    }
296}
297///Field `CMS` reader - Center-aligned mode selection
298pub type CMS_R = crate::FieldReader<u8, CMS_A>;
299/**Center-aligned mode selection
300
301Value on reset: 0*/
302#[derive(Clone, Copy, Debug, PartialEq, Eq)]
303#[repr(u8)]
304pub enum CMS_A {
305    ///0: The counter counts up or down depending on the direction bit
306    EdgeAligned = 0,
307    ///1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
308    CenterAligned1 = 1,
309    ///2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
310    CenterAligned2 = 2,
311    ///3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
312    CenterAligned3 = 3,
313}
314impl From<CMS_A> for u8 {
315    #[inline(always)]
316    fn from(variant: CMS_A) -> Self {
317        variant as _
318    }
319}
320impl CMS_R {
321    ///Get enumerated values variant
322    #[inline(always)]
323    pub fn variant(&self) -> CMS_A {
324        match self.bits {
325            0 => CMS_A::EdgeAligned,
326            1 => CMS_A::CenterAligned1,
327            2 => CMS_A::CenterAligned2,
328            3 => CMS_A::CenterAligned3,
329            _ => unreachable!(),
330        }
331    }
332    ///Checks if the value of the field is `EdgeAligned`
333    #[inline(always)]
334    pub fn is_edge_aligned(&self) -> bool {
335        *self == CMS_A::EdgeAligned
336    }
337    ///Checks if the value of the field is `CenterAligned1`
338    #[inline(always)]
339    pub fn is_center_aligned1(&self) -> bool {
340        *self == CMS_A::CenterAligned1
341    }
342    ///Checks if the value of the field is `CenterAligned2`
343    #[inline(always)]
344    pub fn is_center_aligned2(&self) -> bool {
345        *self == CMS_A::CenterAligned2
346    }
347    ///Checks if the value of the field is `CenterAligned3`
348    #[inline(always)]
349    pub fn is_center_aligned3(&self) -> bool {
350        *self == CMS_A::CenterAligned3
351    }
352}
353///Field `CMS` writer - Center-aligned mode selection
354pub type CMS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR1_SPEC, u8, CMS_A, 2, O>;
355impl<'a, const O: u8> CMS_W<'a, O> {
356    ///The counter counts up or down depending on the direction bit
357    #[inline(always)]
358    pub fn edge_aligned(self) -> &'a mut W {
359        self.variant(CMS_A::EdgeAligned)
360    }
361    ///The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
362    #[inline(always)]
363    pub fn center_aligned1(self) -> &'a mut W {
364        self.variant(CMS_A::CenterAligned1)
365    }
366    ///The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
367    #[inline(always)]
368    pub fn center_aligned2(self) -> &'a mut W {
369        self.variant(CMS_A::CenterAligned2)
370    }
371    ///The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
372    #[inline(always)]
373    pub fn center_aligned3(self) -> &'a mut W {
374        self.variant(CMS_A::CenterAligned3)
375    }
376}
377///Field `ARPE` reader - Auto-reload preload enable
378pub type ARPE_R = crate::BitReader<ARPE_A>;
379/**Auto-reload preload enable
380
381Value on reset: 0*/
382#[derive(Clone, Copy, Debug, PartialEq, Eq)]
383pub enum ARPE_A {
384    ///0: TIMx_APRR register is not buffered
385    Disabled = 0,
386    ///1: TIMx_APRR register is buffered
387    Enabled = 1,
388}
389impl From<ARPE_A> for bool {
390    #[inline(always)]
391    fn from(variant: ARPE_A) -> Self {
392        variant as u8 != 0
393    }
394}
395impl ARPE_R {
396    ///Get enumerated values variant
397    #[inline(always)]
398    pub fn variant(&self) -> ARPE_A {
399        match self.bits {
400            false => ARPE_A::Disabled,
401            true => ARPE_A::Enabled,
402        }
403    }
404    ///Checks if the value of the field is `Disabled`
405    #[inline(always)]
406    pub fn is_disabled(&self) -> bool {
407        *self == ARPE_A::Disabled
408    }
409    ///Checks if the value of the field is `Enabled`
410    #[inline(always)]
411    pub fn is_enabled(&self) -> bool {
412        *self == ARPE_A::Enabled
413    }
414}
415///Field `ARPE` writer - Auto-reload preload enable
416pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, ARPE_A, O>;
417impl<'a, const O: u8> ARPE_W<'a, O> {
418    ///TIMx_APRR register is not buffered
419    #[inline(always)]
420    pub fn disabled(self) -> &'a mut W {
421        self.variant(ARPE_A::Disabled)
422    }
423    ///TIMx_APRR register is buffered
424    #[inline(always)]
425    pub fn enabled(self) -> &'a mut W {
426        self.variant(ARPE_A::Enabled)
427    }
428}
429///Field `CKD` reader - Clock division
430pub type CKD_R = crate::FieldReader<u8, CKD_A>;
431/**Clock division
432
433Value on reset: 0*/
434#[derive(Clone, Copy, Debug, PartialEq, Eq)]
435#[repr(u8)]
436pub enum CKD_A {
437    ///0: t_DTS = t_CK_INT
438    Div1 = 0,
439    ///1: t_DTS = 2 x t_CK_INT
440    Div2 = 1,
441    ///2: t_DTS = 4 x t_CK_INT
442    Div4 = 2,
443}
444impl From<CKD_A> for u8 {
445    #[inline(always)]
446    fn from(variant: CKD_A) -> Self {
447        variant as _
448    }
449}
450impl CKD_R {
451    ///Get enumerated values variant
452    #[inline(always)]
453    pub fn variant(&self) -> Option<CKD_A> {
454        match self.bits {
455            0 => Some(CKD_A::Div1),
456            1 => Some(CKD_A::Div2),
457            2 => Some(CKD_A::Div4),
458            _ => None,
459        }
460    }
461    ///Checks if the value of the field is `Div1`
462    #[inline(always)]
463    pub fn is_div1(&self) -> bool {
464        *self == CKD_A::Div1
465    }
466    ///Checks if the value of the field is `Div2`
467    #[inline(always)]
468    pub fn is_div2(&self) -> bool {
469        *self == CKD_A::Div2
470    }
471    ///Checks if the value of the field is `Div4`
472    #[inline(always)]
473    pub fn is_div4(&self) -> bool {
474        *self == CKD_A::Div4
475    }
476}
477///Field `CKD` writer - Clock division
478pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, CKD_A, 2, O>;
479impl<'a, const O: u8> CKD_W<'a, O> {
480    ///t_DTS = t_CK_INT
481    #[inline(always)]
482    pub fn div1(self) -> &'a mut W {
483        self.variant(CKD_A::Div1)
484    }
485    ///t_DTS = 2 x t_CK_INT
486    #[inline(always)]
487    pub fn div2(self) -> &'a mut W {
488        self.variant(CKD_A::Div2)
489    }
490    ///t_DTS = 4 x t_CK_INT
491    #[inline(always)]
492    pub fn div4(self) -> &'a mut W {
493        self.variant(CKD_A::Div4)
494    }
495}
496impl R {
497    ///Bit 0 - Counter enable
498    #[inline(always)]
499    pub fn cen(&self) -> CEN_R {
500        CEN_R::new((self.bits & 1) != 0)
501    }
502    ///Bit 1 - Update disable
503    #[inline(always)]
504    pub fn udis(&self) -> UDIS_R {
505        UDIS_R::new(((self.bits >> 1) & 1) != 0)
506    }
507    ///Bit 2 - Update request source
508    #[inline(always)]
509    pub fn urs(&self) -> URS_R {
510        URS_R::new(((self.bits >> 2) & 1) != 0)
511    }
512    ///Bit 3 - One-pulse mode
513    #[inline(always)]
514    pub fn opm(&self) -> OPM_R {
515        OPM_R::new(((self.bits >> 3) & 1) != 0)
516    }
517    ///Bit 4 - Direction
518    #[inline(always)]
519    pub fn dir(&self) -> DIR_R {
520        DIR_R::new(((self.bits >> 4) & 1) != 0)
521    }
522    ///Bits 5:6 - Center-aligned mode selection
523    #[inline(always)]
524    pub fn cms(&self) -> CMS_R {
525        CMS_R::new(((self.bits >> 5) & 3) as u8)
526    }
527    ///Bit 7 - Auto-reload preload enable
528    #[inline(always)]
529    pub fn arpe(&self) -> ARPE_R {
530        ARPE_R::new(((self.bits >> 7) & 1) != 0)
531    }
532    ///Bits 8:9 - Clock division
533    #[inline(always)]
534    pub fn ckd(&self) -> CKD_R {
535        CKD_R::new(((self.bits >> 8) & 3) as u8)
536    }
537}
538impl W {
539    ///Bit 0 - Counter enable
540    #[inline(always)]
541    #[must_use]
542    pub fn cen(&mut self) -> CEN_W<0> {
543        CEN_W::new(self)
544    }
545    ///Bit 1 - Update disable
546    #[inline(always)]
547    #[must_use]
548    pub fn udis(&mut self) -> UDIS_W<1> {
549        UDIS_W::new(self)
550    }
551    ///Bit 2 - Update request source
552    #[inline(always)]
553    #[must_use]
554    pub fn urs(&mut self) -> URS_W<2> {
555        URS_W::new(self)
556    }
557    ///Bit 3 - One-pulse mode
558    #[inline(always)]
559    #[must_use]
560    pub fn opm(&mut self) -> OPM_W<3> {
561        OPM_W::new(self)
562    }
563    ///Bit 4 - Direction
564    #[inline(always)]
565    #[must_use]
566    pub fn dir(&mut self) -> DIR_W<4> {
567        DIR_W::new(self)
568    }
569    ///Bits 5:6 - Center-aligned mode selection
570    #[inline(always)]
571    #[must_use]
572    pub fn cms(&mut self) -> CMS_W<5> {
573        CMS_W::new(self)
574    }
575    ///Bit 7 - Auto-reload preload enable
576    #[inline(always)]
577    #[must_use]
578    pub fn arpe(&mut self) -> ARPE_W<7> {
579        ARPE_W::new(self)
580    }
581    ///Bits 8:9 - Clock division
582    #[inline(always)]
583    #[must_use]
584    pub fn ckd(&mut self) -> CKD_W<8> {
585        CKD_W::new(self)
586    }
587    ///Writes raw bits to the register.
588    #[inline(always)]
589    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
590        self.0.bits(bits);
591        self
592    }
593}
594/**control register 1
595
596This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
597
598For information about available fields see [cr1](index.html) module*/
599pub struct CR1_SPEC;
600impl crate::RegisterSpec for CR1_SPEC {
601    type Ux = u32;
602}
603///`read()` method returns [cr1::R](R) reader structure
604impl crate::Readable for CR1_SPEC {
605    type Reader = R;
606}
607///`write(|w| ..)` method takes [cr1::W](W) writer structure
608impl crate::Writable for CR1_SPEC {
609    type Writer = W;
610    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
611    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
612}
613///`reset()` method sets CR1 to value 0
614impl crate::Resettable for CR1_SPEC {
615    const RESET_VALUE: Self::Ux = 0;
616}
py32f0/py32f003/tim3/cr1.rs

py32f0/py32f003/tim3/
cr1.rs
