py32f0/py32f003/tim1/
ccmr2_output.rs

1///Register `CCMR2_Output` reader
2pub struct R(crate::R<CCMR2_OUTPUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCMR2_OUTPUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCMR2_OUTPUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCMR2_OUTPUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CCMR2_Output` writer
17pub struct W(crate::W<CCMR2_OUTPUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCMR2_OUTPUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCMR2_OUTPUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCMR2_OUTPUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CC3S` reader - Capture/Compare 3 selection
38pub type CC3S_R = crate::FieldReader<u8, CC3S_A>;
39/**Capture/Compare 3 selection
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u8)]
44pub enum CC3S_A {
45    ///0: CCx channel is configured as output
46    Output = 0,
47}
48impl From<CC3S_A> for u8 {
49    #[inline(always)]
50    fn from(variant: CC3S_A) -> Self {
51        variant as _
52    }
53}
54impl CC3S_R {
55    ///Get enumerated values variant
56    #[inline(always)]
57    pub fn variant(&self) -> Option<CC3S_A> {
58        match self.bits {
59            0 => Some(CC3S_A::Output),
60            _ => None,
61        }
62    }
63    ///Checks if the value of the field is `Output`
64    #[inline(always)]
65    pub fn is_output(&self) -> bool {
66        *self == CC3S_A::Output
67    }
68}
69///Field `CC3S` writer - Capture/Compare 3 selection
70pub type CC3S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR2_OUTPUT_SPEC, u8, CC3S_A, 2, O>;
71impl<'a, const O: u8> CC3S_W<'a, O> {
72    ///CCx channel is configured as output
73    #[inline(always)]
74    pub fn output(self) -> &'a mut W {
75        self.variant(CC3S_A::Output)
76    }
77}
78///Field `OC3FE` reader - Output compare 3 fast enable
79pub type OC3FE_R = crate::BitReader<bool>;
80///Field `OC3FE` writer - Output compare 3 fast enable
81pub type OC3FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
82///Field `OC3PE` reader - Output compare 3 preload enable
83pub type OC3PE_R = crate::BitReader<OC3PE_A>;
84/**Output compare 3 preload enable
85
86Value on reset: 0*/
87#[derive(Clone, Copy, Debug, PartialEq, Eq)]
88pub enum OC3PE_A {
89    ///0: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
90    Disabled = 0,
91    ///1: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
92    Enabled = 1,
93}
94impl From<OC3PE_A> for bool {
95    #[inline(always)]
96    fn from(variant: OC3PE_A) -> Self {
97        variant as u8 != 0
98    }
99}
100impl OC3PE_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub fn variant(&self) -> OC3PE_A {
104        match self.bits {
105            false => OC3PE_A::Disabled,
106            true => OC3PE_A::Enabled,
107        }
108    }
109    ///Checks if the value of the field is `Disabled`
110    #[inline(always)]
111    pub fn is_disabled(&self) -> bool {
112        *self == OC3PE_A::Disabled
113    }
114    ///Checks if the value of the field is `Enabled`
115    #[inline(always)]
116    pub fn is_enabled(&self) -> bool {
117        *self == OC3PE_A::Enabled
118    }
119}
120///Field `OC3PE` writer - Output compare 3 preload enable
121pub type OC3PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, OC3PE_A, O>;
122impl<'a, const O: u8> OC3PE_W<'a, O> {
123    ///Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
124    #[inline(always)]
125    pub fn disabled(self) -> &'a mut W {
126        self.variant(OC3PE_A::Disabled)
127    }
128    ///Preload register on CCRx enabled. Preload value is loaded into active register on each update event
129    #[inline(always)]
130    pub fn enabled(self) -> &'a mut W {
131        self.variant(OC3PE_A::Enabled)
132    }
133}
134///Field `OC3M` reader - Output compare 3 mode
135pub type OC3M_R = crate::FieldReader<u8, OC3M_A>;
136/**Output compare 3 mode
137
138Value on reset: 0*/
139#[derive(Clone, Copy, Debug, PartialEq, Eq)]
140#[repr(u8)]
141pub enum OC3M_A {
142    ///0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
143    Frozen = 0,
144    ///1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
145    ActiveOnMatch = 1,
146    ///2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
147    InactiveOnMatch = 2,
148    ///3: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
149    Toggle = 3,
150    ///4: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
151    ForceInactive = 4,
152    ///5: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
153    ForceActive = 5,
154    ///6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
155    PwmMode1 = 6,
156    ///7: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
157    PwmMode2 = 7,
158}
159impl From<OC3M_A> for u8 {
160    #[inline(always)]
161    fn from(variant: OC3M_A) -> Self {
162        variant as _
163    }
164}
165impl OC3M_R {
166    ///Get enumerated values variant
167    #[inline(always)]
168    pub fn variant(&self) -> OC3M_A {
169        match self.bits {
170            0 => OC3M_A::Frozen,
171            1 => OC3M_A::ActiveOnMatch,
172            2 => OC3M_A::InactiveOnMatch,
173            3 => OC3M_A::Toggle,
174            4 => OC3M_A::ForceInactive,
175            5 => OC3M_A::ForceActive,
176            6 => OC3M_A::PwmMode1,
177            7 => OC3M_A::PwmMode2,
178            _ => unreachable!(),
179        }
180    }
181    ///Checks if the value of the field is `Frozen`
182    #[inline(always)]
183    pub fn is_frozen(&self) -> bool {
184        *self == OC3M_A::Frozen
185    }
186    ///Checks if the value of the field is `ActiveOnMatch`
187    #[inline(always)]
188    pub fn is_active_on_match(&self) -> bool {
189        *self == OC3M_A::ActiveOnMatch
190    }
191    ///Checks if the value of the field is `InactiveOnMatch`
192    #[inline(always)]
193    pub fn is_inactive_on_match(&self) -> bool {
194        *self == OC3M_A::InactiveOnMatch
195    }
196    ///Checks if the value of the field is `Toggle`
197    #[inline(always)]
198    pub fn is_toggle(&self) -> bool {
199        *self == OC3M_A::Toggle
200    }
201    ///Checks if the value of the field is `ForceInactive`
202    #[inline(always)]
203    pub fn is_force_inactive(&self) -> bool {
204        *self == OC3M_A::ForceInactive
205    }
206    ///Checks if the value of the field is `ForceActive`
207    #[inline(always)]
208    pub fn is_force_active(&self) -> bool {
209        *self == OC3M_A::ForceActive
210    }
211    ///Checks if the value of the field is `PwmMode1`
212    #[inline(always)]
213    pub fn is_pwm_mode1(&self) -> bool {
214        *self == OC3M_A::PwmMode1
215    }
216    ///Checks if the value of the field is `PwmMode2`
217    #[inline(always)]
218    pub fn is_pwm_mode2(&self) -> bool {
219        *self == OC3M_A::PwmMode2
220    }
221}
222///Field `OC3M` writer - Output compare 3 mode
223pub type OC3M_W<'a, const O: u8> =
224    crate::FieldWriterSafe<'a, u32, CCMR2_OUTPUT_SPEC, u8, OC3M_A, 3, O>;
225impl<'a, const O: u8> OC3M_W<'a, O> {
226    ///The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
227    #[inline(always)]
228    pub fn frozen(self) -> &'a mut W {
229        self.variant(OC3M_A::Frozen)
230    }
231    ///Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
232    #[inline(always)]
233    pub fn active_on_match(self) -> &'a mut W {
234        self.variant(OC3M_A::ActiveOnMatch)
235    }
236    ///Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
237    #[inline(always)]
238    pub fn inactive_on_match(self) -> &'a mut W {
239        self.variant(OC3M_A::InactiveOnMatch)
240    }
241    ///OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
242    #[inline(always)]
243    pub fn toggle(self) -> &'a mut W {
244        self.variant(OC3M_A::Toggle)
245    }
246    ///OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
247    #[inline(always)]
248    pub fn force_inactive(self) -> &'a mut W {
249        self.variant(OC3M_A::ForceInactive)
250    }
251    ///OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
252    #[inline(always)]
253    pub fn force_active(self) -> &'a mut W {
254        self.variant(OC3M_A::ForceActive)
255    }
256    ///In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
257    #[inline(always)]
258    pub fn pwm_mode1(self) -> &'a mut W {
259        self.variant(OC3M_A::PwmMode1)
260    }
261    ///Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
262    #[inline(always)]
263    pub fn pwm_mode2(self) -> &'a mut W {
264        self.variant(OC3M_A::PwmMode2)
265    }
266}
267///Field `OC3CE` reader - Output compare 3 clear enable
268pub type OC3CE_R = crate::BitReader<bool>;
269///Field `OC3CE` writer - Output compare 3 clear enable
270pub type OC3CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
271///Field `CC4S` reader - Capture/Compare 4 selection
272pub use CC3S_R as CC4S_R;
273///Field `CC4S` writer - Capture/Compare 4 selection
274pub use CC3S_W as CC4S_W;
275///Field `OC4FE` reader - Output compare 4 fast enable
276pub type OC4FE_R = crate::BitReader<bool>;
277///Field `OC4FE` writer - Output compare 4 fast enable
278pub type OC4FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
279///Field `OC4M` reader - Output compare 4 mode
280pub use OC3M_R as OC4M_R;
281///Field `OC4M` writer - Output compare 4 mode
282pub use OC3M_W as OC4M_W;
283///Field `OC4PE` reader - Output compare 4 preload enable
284pub use OC3PE_R as OC4PE_R;
285///Field `OC4PE` writer - Output compare 4 preload enable
286pub use OC3PE_W as OC4PE_W;
287///Field `OC4CE` reader - Output compare 4 clear enable
288pub type OC4CE_R = crate::BitReader<bool>;
289///Field `OC4CE` writer - Output compare 4 clear enable
290pub type OC4CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR2_OUTPUT_SPEC, bool, O>;
291impl R {
292    ///Bits 0:1 - Capture/Compare 3 selection
293    #[inline(always)]
294    pub fn cc3s(&self) -> CC3S_R {
295        CC3S_R::new((self.bits & 3) as u8)
296    }
297    ///Bit 2 - Output compare 3 fast enable
298    #[inline(always)]
299    pub fn oc3fe(&self) -> OC3FE_R {
300        OC3FE_R::new(((self.bits >> 2) & 1) != 0)
301    }
302    ///Bit 3 - Output compare 3 preload enable
303    #[inline(always)]
304    pub fn oc3pe(&self) -> OC3PE_R {
305        OC3PE_R::new(((self.bits >> 3) & 1) != 0)
306    }
307    ///Bits 4:6 - Output compare 3 mode
308    #[inline(always)]
309    pub fn oc3m(&self) -> OC3M_R {
310        OC3M_R::new(((self.bits >> 4) & 7) as u8)
311    }
312    ///Bit 7 - Output compare 3 clear enable
313    #[inline(always)]
314    pub fn oc3ce(&self) -> OC3CE_R {
315        OC3CE_R::new(((self.bits >> 7) & 1) != 0)
316    }
317    ///Bits 8:9 - Capture/Compare 4 selection
318    #[inline(always)]
319    pub fn cc4s(&self) -> CC4S_R {
320        CC4S_R::new(((self.bits >> 8) & 3) as u8)
321    }
322    ///Bit 10 - Output compare 4 fast enable
323    #[inline(always)]
324    pub fn oc4fe(&self) -> OC4FE_R {
325        OC4FE_R::new(((self.bits >> 10) & 1) != 0)
326    }
327    ///Bit 11 - Output compare 4 preload enable
328    #[inline(always)]
329    pub fn oc4pe(&self) -> OC4PE_R {
330        OC4PE_R::new(((self.bits >> 11) & 1) != 0)
331    }
332    ///Bits 12:14 - Output compare 4 mode
333    #[inline(always)]
334    pub fn oc4m(&self) -> OC4M_R {
335        OC4M_R::new(((self.bits >> 12) & 7) as u8)
336    }
337    ///Bit 15 - Output compare 4 clear enable
338    #[inline(always)]
339    pub fn oc4ce(&self) -> OC4CE_R {
340        OC4CE_R::new(((self.bits >> 15) & 1) != 0)
341    }
342}
343impl W {
344    ///Bits 0:1 - Capture/Compare 3 selection
345    #[inline(always)]
346    #[must_use]
347    pub fn cc3s(&mut self) -> CC3S_W<0> {
348        CC3S_W::new(self)
349    }
350    ///Bit 2 - Output compare 3 fast enable
351    #[inline(always)]
352    #[must_use]
353    pub fn oc3fe(&mut self) -> OC3FE_W<2> {
354        OC3FE_W::new(self)
355    }
356    ///Bit 3 - Output compare 3 preload enable
357    #[inline(always)]
358    #[must_use]
359    pub fn oc3pe(&mut self) -> OC3PE_W<3> {
360        OC3PE_W::new(self)
361    }
362    ///Bits 4:6 - Output compare 3 mode
363    #[inline(always)]
364    #[must_use]
365    pub fn oc3m(&mut self) -> OC3M_W<4> {
366        OC3M_W::new(self)
367    }
368    ///Bit 7 - Output compare 3 clear enable
369    #[inline(always)]
370    #[must_use]
371    pub fn oc3ce(&mut self) -> OC3CE_W<7> {
372        OC3CE_W::new(self)
373    }
374    ///Bits 8:9 - Capture/Compare 4 selection
375    #[inline(always)]
376    #[must_use]
377    pub fn cc4s(&mut self) -> CC4S_W<8> {
378        CC4S_W::new(self)
379    }
380    ///Bit 10 - Output compare 4 fast enable
381    #[inline(always)]
382    #[must_use]
383    pub fn oc4fe(&mut self) -> OC4FE_W<10> {
384        OC4FE_W::new(self)
385    }
386    ///Bit 11 - Output compare 4 preload enable
387    #[inline(always)]
388    #[must_use]
389    pub fn oc4pe(&mut self) -> OC4PE_W<11> {
390        OC4PE_W::new(self)
391    }
392    ///Bits 12:14 - Output compare 4 mode
393    #[inline(always)]
394    #[must_use]
395    pub fn oc4m(&mut self) -> OC4M_W<12> {
396        OC4M_W::new(self)
397    }
398    ///Bit 15 - Output compare 4 clear enable
399    #[inline(always)]
400    #[must_use]
401    pub fn oc4ce(&mut self) -> OC4CE_W<15> {
402        OC4CE_W::new(self)
403    }
404    ///Writes raw bits to the register.
405    #[inline(always)]
406    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
407        self.0.bits(bits);
408        self
409    }
410}
411/**capture/compare mode register (output mode)
412
413This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
414
415For information about available fields see [ccmr2_output](index.html) module*/
416pub struct CCMR2_OUTPUT_SPEC;
417impl crate::RegisterSpec for CCMR2_OUTPUT_SPEC {
418    type Ux = u32;
419}
420///`read()` method returns [ccmr2_output::R](R) reader structure
421impl crate::Readable for CCMR2_OUTPUT_SPEC {
422    type Reader = R;
423}
424///`write(|w| ..)` method takes [ccmr2_output::W](W) writer structure
425impl crate::Writable for CCMR2_OUTPUT_SPEC {
426    type Writer = W;
427    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
428    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
429}
430///`reset()` method sets CCMR2_Output to value 0
431impl crate::Resettable for CCMR2_OUTPUT_SPEC {
432    const RESET_VALUE: Self::Ux = 0;
433}
py32f0/py32f003/tim1/ccmr2_output.rs

py32f0/py32f003/tim1/
ccmr2_output.rs
