py32f0/py32f003/rcc/
icscr.rs

1///Register `ICSCR` reader
2pub struct R(crate::R<ICSCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ICSCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ICSCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ICSCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `ICSCR` writer
17pub struct W(crate::W<ICSCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ICSCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ICSCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ICSCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `HSI_TRIM` reader - HSI clock trimming
38pub type HSI_TRIM_R = crate::FieldReader<u16, u16>;
39///Field `HSI_TRIM` writer - HSI clock trimming
40pub type HSI_TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ICSCR_SPEC, u16, u16, 13, O>;
41///Field `HSI_FS` reader - HSI frequency selection
42pub type HSI_FS_R = crate::FieldReader<u8, HSI_FS_A>;
43/**HSI frequency selection
44
45Value on reset: 0*/
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47#[repr(u8)]
48pub enum HSI_FS_A {
49    ///0: Select internal 4 MHz oscilator
50    Freq4mhz = 0,
51    ///1: Select internal 8 MHz oscilator
52    Freq8mhz = 1,
53    ///2: Select internal 16 MHz oscilator
54    Freq16mhz = 2,
55    ///3: Select internal 22.12 MHz oscilator
56    Freq2212mhz = 3,
57    ///4: Select internal 24 MHz oscilator
58    Freq24mhz = 4,
59}
60impl From<HSI_FS_A> for u8 {
61    #[inline(always)]
62    fn from(variant: HSI_FS_A) -> Self {
63        variant as _
64    }
65}
66impl HSI_FS_R {
67    ///Get enumerated values variant
68    #[inline(always)]
69    pub fn variant(&self) -> Option<HSI_FS_A> {
70        match self.bits {
71            0 => Some(HSI_FS_A::Freq4mhz),
72            1 => Some(HSI_FS_A::Freq8mhz),
73            2 => Some(HSI_FS_A::Freq16mhz),
74            3 => Some(HSI_FS_A::Freq2212mhz),
75            4 => Some(HSI_FS_A::Freq24mhz),
76            _ => None,
77        }
78    }
79    ///Checks if the value of the field is `Freq4mhz`
80    #[inline(always)]
81    pub fn is_freq4mhz(&self) -> bool {
82        *self == HSI_FS_A::Freq4mhz
83    }
84    ///Checks if the value of the field is `Freq8mhz`
85    #[inline(always)]
86    pub fn is_freq8mhz(&self) -> bool {
87        *self == HSI_FS_A::Freq8mhz
88    }
89    ///Checks if the value of the field is `Freq16mhz`
90    #[inline(always)]
91    pub fn is_freq16mhz(&self) -> bool {
92        *self == HSI_FS_A::Freq16mhz
93    }
94    ///Checks if the value of the field is `Freq2212mhz`
95    #[inline(always)]
96    pub fn is_freq22_12mhz(&self) -> bool {
97        *self == HSI_FS_A::Freq2212mhz
98    }
99    ///Checks if the value of the field is `Freq24mhz`
100    #[inline(always)]
101    pub fn is_freq24mhz(&self) -> bool {
102        *self == HSI_FS_A::Freq24mhz
103    }
104}
105///Field `HSI_FS` writer - HSI frequency selection
106pub type HSI_FS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ICSCR_SPEC, u8, HSI_FS_A, 3, O>;
107impl<'a, const O: u8> HSI_FS_W<'a, O> {
108    ///Select internal 4 MHz oscilator
109    #[inline(always)]
110    pub fn freq4mhz(self) -> &'a mut W {
111        self.variant(HSI_FS_A::Freq4mhz)
112    }
113    ///Select internal 8 MHz oscilator
114    #[inline(always)]
115    pub fn freq8mhz(self) -> &'a mut W {
116        self.variant(HSI_FS_A::Freq8mhz)
117    }
118    ///Select internal 16 MHz oscilator
119    #[inline(always)]
120    pub fn freq16mhz(self) -> &'a mut W {
121        self.variant(HSI_FS_A::Freq16mhz)
122    }
123    ///Select internal 22.12 MHz oscilator
124    #[inline(always)]
125    pub fn freq22_12mhz(self) -> &'a mut W {
126        self.variant(HSI_FS_A::Freq2212mhz)
127    }
128    ///Select internal 24 MHz oscilator
129    #[inline(always)]
130    pub fn freq24mhz(self) -> &'a mut W {
131        self.variant(HSI_FS_A::Freq24mhz)
132    }
133}
134///Field `LSI_TRIM` reader - LSI clock trimming
135pub type LSI_TRIM_R = crate::FieldReader<u16, u16>;
136///Field `LSI_TRIM` writer - LSI clock trimming
137pub type LSI_TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ICSCR_SPEC, u16, u16, 9, O>;
138///Field `LSI_STARTUP` reader - LSI startup time
139pub type LSI_STARTUP_R = crate::FieldReader<u8, LSI_STARTUP_A>;
140/**LSI startup time
141
142Value on reset: 0*/
143#[derive(Clone, Copy, Debug, PartialEq, Eq)]
144#[repr(u8)]
145pub enum LSI_STARTUP_A {
146    ///0: 4 LSI cycles for startup
147    Cycles4 = 0,
148    ///1: 16 LSI cycles for startup
149    Cycles16 = 1,
150    ///2: 64 LSI cycles for startup
151    Cycles64 = 2,
152    ///3: 256 LSI cycles for startup
153    Cycles256 = 3,
154}
155impl From<LSI_STARTUP_A> for u8 {
156    #[inline(always)]
157    fn from(variant: LSI_STARTUP_A) -> Self {
158        variant as _
159    }
160}
161impl LSI_STARTUP_R {
162    ///Get enumerated values variant
163    #[inline(always)]
164    pub fn variant(&self) -> LSI_STARTUP_A {
165        match self.bits {
166            0 => LSI_STARTUP_A::Cycles4,
167            1 => LSI_STARTUP_A::Cycles16,
168            2 => LSI_STARTUP_A::Cycles64,
169            3 => LSI_STARTUP_A::Cycles256,
170            _ => unreachable!(),
171        }
172    }
173    ///Checks if the value of the field is `Cycles4`
174    #[inline(always)]
175    pub fn is_cycles4(&self) -> bool {
176        *self == LSI_STARTUP_A::Cycles4
177    }
178    ///Checks if the value of the field is `Cycles16`
179    #[inline(always)]
180    pub fn is_cycles16(&self) -> bool {
181        *self == LSI_STARTUP_A::Cycles16
182    }
183    ///Checks if the value of the field is `Cycles64`
184    #[inline(always)]
185    pub fn is_cycles64(&self) -> bool {
186        *self == LSI_STARTUP_A::Cycles64
187    }
188    ///Checks if the value of the field is `Cycles256`
189    #[inline(always)]
190    pub fn is_cycles256(&self) -> bool {
191        *self == LSI_STARTUP_A::Cycles256
192    }
193}
194///Field `LSI_STARTUP` writer - LSI startup time
195pub type LSI_STARTUP_W<'a, const O: u8> =
196    crate::FieldWriterSafe<'a, u32, ICSCR_SPEC, u8, LSI_STARTUP_A, 2, O>;
197impl<'a, const O: u8> LSI_STARTUP_W<'a, O> {
198    ///4 LSI cycles for startup
199    #[inline(always)]
200    pub fn cycles4(self) -> &'a mut W {
201        self.variant(LSI_STARTUP_A::Cycles4)
202    }
203    ///16 LSI cycles for startup
204    #[inline(always)]
205    pub fn cycles16(self) -> &'a mut W {
206        self.variant(LSI_STARTUP_A::Cycles16)
207    }
208    ///64 LSI cycles for startup
209    #[inline(always)]
210    pub fn cycles64(self) -> &'a mut W {
211        self.variant(LSI_STARTUP_A::Cycles64)
212    }
213    ///256 LSI cycles for startup
214    #[inline(always)]
215    pub fn cycles256(self) -> &'a mut W {
216        self.variant(LSI_STARTUP_A::Cycles256)
217    }
218}
219impl R {
220    ///Bits 0:12 - HSI clock trimming
221    #[inline(always)]
222    pub fn hsi_trim(&self) -> HSI_TRIM_R {
223        HSI_TRIM_R::new((self.bits & 0x1fff) as u16)
224    }
225    ///Bits 13:15 - HSI frequency selection
226    #[inline(always)]
227    pub fn hsi_fs(&self) -> HSI_FS_R {
228        HSI_FS_R::new(((self.bits >> 13) & 7) as u8)
229    }
230    ///Bits 16:24 - LSI clock trimming
231    #[inline(always)]
232    pub fn lsi_trim(&self) -> LSI_TRIM_R {
233        LSI_TRIM_R::new(((self.bits >> 16) & 0x01ff) as u16)
234    }
235    ///Bits 26:27 - LSI startup time
236    #[inline(always)]
237    pub fn lsi_startup(&self) -> LSI_STARTUP_R {
238        LSI_STARTUP_R::new(((self.bits >> 26) & 3) as u8)
239    }
240}
241impl W {
242    ///Bits 0:12 - HSI clock trimming
243    #[inline(always)]
244    #[must_use]
245    pub fn hsi_trim(&mut self) -> HSI_TRIM_W<0> {
246        HSI_TRIM_W::new(self)
247    }
248    ///Bits 13:15 - HSI frequency selection
249    #[inline(always)]
250    #[must_use]
251    pub fn hsi_fs(&mut self) -> HSI_FS_W<13> {
252        HSI_FS_W::new(self)
253    }
254    ///Bits 16:24 - LSI clock trimming
255    #[inline(always)]
256    #[must_use]
257    pub fn lsi_trim(&mut self) -> LSI_TRIM_W<16> {
258        LSI_TRIM_W::new(self)
259    }
260    ///Bits 26:27 - LSI startup time
261    #[inline(always)]
262    #[must_use]
263    pub fn lsi_startup(&mut self) -> LSI_STARTUP_W<26> {
264        LSI_STARTUP_W::new(self)
265    }
266    ///Writes raw bits to the register.
267    #[inline(always)]
268    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
269        self.0.bits(bits);
270        self
271    }
272}
273/**Internal clock sources calibration register
274
275This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
276
277For information about available fields see [icscr](index.html) module*/
278pub struct ICSCR_SPEC;
279impl crate::RegisterSpec for ICSCR_SPEC {
280    type Ux = u32;
281}
282///`read()` method returns [icscr::R](R) reader structure
283impl crate::Readable for ICSCR_SPEC {
284    type Reader = R;
285}
286///`write(|w| ..)` method takes [icscr::W](W) writer structure
287impl crate::Writable for ICSCR_SPEC {
288    type Writer = W;
289    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
290    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
291}
292///`reset()` method sets ICSCR to value 0x1000_0000
293impl crate::Resettable for ICSCR_SPEC {
294    const RESET_VALUE: Self::Ux = 0x1000_0000;
295}
py32f0/py32f003/rcc/icscr.rs

py32f0/py32f003/rcc/
icscr.rs
