py32f0/py32f003/rcc/
cr.rs

1///Register `CR` reader
2pub struct R(crate::R<CR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR` writer
17pub struct W(crate::W<CR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `HSION` reader - HSI16 clock enable
38pub type HSION_R = crate::BitReader<HSION_A>;
39/**HSI16 clock enable
40
41Value on reset: 1*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum HSION_A {
44    ///0: Clock disabled
45    Off = 0,
46    ///1: Clock enabled
47    On = 1,
48}
49impl From<HSION_A> for bool {
50    #[inline(always)]
51    fn from(variant: HSION_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl HSION_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> HSION_A {
59        match self.bits {
60            false => HSION_A::Off,
61            true => HSION_A::On,
62        }
63    }
64    ///Checks if the value of the field is `Off`
65    #[inline(always)]
66    pub fn is_off(&self) -> bool {
67        *self == HSION_A::Off
68    }
69    ///Checks if the value of the field is `On`
70    #[inline(always)]
71    pub fn is_on(&self) -> bool {
72        *self == HSION_A::On
73    }
74}
75///Field `HSION` writer - HSI16 clock enable
76pub type HSION_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, HSION_A, O>;
77impl<'a, const O: u8> HSION_W<'a, O> {
78    ///Clock disabled
79    #[inline(always)]
80    pub fn off(self) -> &'a mut W {
81        self.variant(HSION_A::Off)
82    }
83    ///Clock enabled
84    #[inline(always)]
85    pub fn on(self) -> &'a mut W {
86        self.variant(HSION_A::On)
87    }
88}
89///Field `HSIKERON` reader - HSI16 always enable for peripheral kernels
90pub use HSION_R as HSIKERON_R;
91///Field `HSIKERON` writer - HSI16 always enable for peripheral kernels
92pub use HSION_W as HSIKERON_W;
93///Field `HSIRDY` reader - HSI16 clock ready flag
94pub type HSIRDY_R = crate::BitReader<HSIRDYR_A>;
95/**HSI16 clock ready flag
96
97Value on reset: 0*/
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99pub enum HSIRDYR_A {
100    ///0: Oscillator is not stable
101    NotReady = 0,
102    ///1: Oscillator is stable
103    Ready = 1,
104}
105impl From<HSIRDYR_A> for bool {
106    #[inline(always)]
107    fn from(variant: HSIRDYR_A) -> Self {
108        variant as u8 != 0
109    }
110}
111impl HSIRDY_R {
112    ///Get enumerated values variant
113    #[inline(always)]
114    pub fn variant(&self) -> HSIRDYR_A {
115        match self.bits {
116            false => HSIRDYR_A::NotReady,
117            true => HSIRDYR_A::Ready,
118        }
119    }
120    ///Checks if the value of the field is `NotReady`
121    #[inline(always)]
122    pub fn is_not_ready(&self) -> bool {
123        *self == HSIRDYR_A::NotReady
124    }
125    ///Checks if the value of the field is `Ready`
126    #[inline(always)]
127    pub fn is_ready(&self) -> bool {
128        *self == HSIRDYR_A::Ready
129    }
130}
131///Field `HSIRDY` writer - HSI16 clock ready flag
132pub type HSIRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, HSIRDYR_A, O>;
133impl<'a, const O: u8> HSIRDY_W<'a, O> {
134    ///Oscillator is not stable
135    #[inline(always)]
136    pub fn not_ready(self) -> &'a mut W {
137        self.variant(HSIRDYR_A::NotReady)
138    }
139    ///Oscillator is stable
140    #[inline(always)]
141    pub fn ready(self) -> &'a mut W {
142        self.variant(HSIRDYR_A::Ready)
143    }
144}
145///Field `HSIDIV` reader - HSI16 clock division factor
146pub type HSIDIV_R = crate::FieldReader<u8, HSIDIV_A>;
147/**HSI16 clock division factor
148
149Value on reset: 0*/
150#[derive(Clone, Copy, Debug, PartialEq, Eq)]
151#[repr(u8)]
152pub enum HSIDIV_A {
153    ///0: no HSI division requested
154    NotDivided = 0,
155    ///1: HSI division by 2 requested
156    Div2 = 1,
157    ///2: HSI division by 4 requested
158    Div4 = 2,
159    ///3: HSI division by 8 requested
160    Div8 = 3,
161    ///4: HSI division by 16 requested
162    Div16 = 4,
163    ///5: HSI division by 32 requested
164    Div32 = 5,
165    ///6: HSI division by 64 requested
166    Div64 = 6,
167    ///7: HSI division by 128 requested
168    Div128 = 7,
169}
170impl From<HSIDIV_A> for u8 {
171    #[inline(always)]
172    fn from(variant: HSIDIV_A) -> Self {
173        variant as _
174    }
175}
176impl HSIDIV_R {
177    ///Get enumerated values variant
178    #[inline(always)]
179    pub fn variant(&self) -> HSIDIV_A {
180        match self.bits {
181            0 => HSIDIV_A::NotDivided,
182            1 => HSIDIV_A::Div2,
183            2 => HSIDIV_A::Div4,
184            3 => HSIDIV_A::Div8,
185            4 => HSIDIV_A::Div16,
186            5 => HSIDIV_A::Div32,
187            6 => HSIDIV_A::Div64,
188            7 => HSIDIV_A::Div128,
189            _ => unreachable!(),
190        }
191    }
192    ///Checks if the value of the field is `NotDivided`
193    #[inline(always)]
194    pub fn is_not_divided(&self) -> bool {
195        *self == HSIDIV_A::NotDivided
196    }
197    ///Checks if the value of the field is `Div2`
198    #[inline(always)]
199    pub fn is_div2(&self) -> bool {
200        *self == HSIDIV_A::Div2
201    }
202    ///Checks if the value of the field is `Div4`
203    #[inline(always)]
204    pub fn is_div4(&self) -> bool {
205        *self == HSIDIV_A::Div4
206    }
207    ///Checks if the value of the field is `Div8`
208    #[inline(always)]
209    pub fn is_div8(&self) -> bool {
210        *self == HSIDIV_A::Div8
211    }
212    ///Checks if the value of the field is `Div16`
213    #[inline(always)]
214    pub fn is_div16(&self) -> bool {
215        *self == HSIDIV_A::Div16
216    }
217    ///Checks if the value of the field is `Div32`
218    #[inline(always)]
219    pub fn is_div32(&self) -> bool {
220        *self == HSIDIV_A::Div32
221    }
222    ///Checks if the value of the field is `Div64`
223    #[inline(always)]
224    pub fn is_div64(&self) -> bool {
225        *self == HSIDIV_A::Div64
226    }
227    ///Checks if the value of the field is `Div128`
228    #[inline(always)]
229    pub fn is_div128(&self) -> bool {
230        *self == HSIDIV_A::Div128
231    }
232}
233///Field `HSIDIV` writer - HSI16 clock division factor
234pub type HSIDIV_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR_SPEC, u8, HSIDIV_A, 3, O>;
235impl<'a, const O: u8> HSIDIV_W<'a, O> {
236    ///no HSI division requested
237    #[inline(always)]
238    pub fn not_divided(self) -> &'a mut W {
239        self.variant(HSIDIV_A::NotDivided)
240    }
241    ///HSI division by 2 requested
242    #[inline(always)]
243    pub fn div2(self) -> &'a mut W {
244        self.variant(HSIDIV_A::Div2)
245    }
246    ///HSI division by 4 requested
247    #[inline(always)]
248    pub fn div4(self) -> &'a mut W {
249        self.variant(HSIDIV_A::Div4)
250    }
251    ///HSI division by 8 requested
252    #[inline(always)]
253    pub fn div8(self) -> &'a mut W {
254        self.variant(HSIDIV_A::Div8)
255    }
256    ///HSI division by 16 requested
257    #[inline(always)]
258    pub fn div16(self) -> &'a mut W {
259        self.variant(HSIDIV_A::Div16)
260    }
261    ///HSI division by 32 requested
262    #[inline(always)]
263    pub fn div32(self) -> &'a mut W {
264        self.variant(HSIDIV_A::Div32)
265    }
266    ///HSI division by 64 requested
267    #[inline(always)]
268    pub fn div64(self) -> &'a mut W {
269        self.variant(HSIDIV_A::Div64)
270    }
271    ///HSI division by 128 requested
272    #[inline(always)]
273    pub fn div128(self) -> &'a mut W {
274        self.variant(HSIDIV_A::Div128)
275    }
276}
277///Field `HSEON` reader - HSE clock enable
278pub use HSION_R as HSEON_R;
279///Field `HSEON` writer - HSE clock enable
280pub use HSION_W as HSEON_W;
281///Field `HSERDY` reader - HSE clock ready flag
282pub use HSIRDY_R as HSERDY_R;
283///Field `HSERDY` writer - HSE clock ready flag
284pub use HSIRDY_W as HSERDY_W;
285///Field `HSEBYP` reader - HSE crystal oscillator bypass
286pub type HSEBYP_R = crate::BitReader<HSEBYP_A>;
287/**HSE crystal oscillator bypass
288
289Value on reset: 0*/
290#[derive(Clone, Copy, Debug, PartialEq, Eq)]
291pub enum HSEBYP_A {
292    ///0: HSE oscillator not bypassed
293    NotBypassed = 0,
294    ///1: HSE oscillator bypassed
295    Bypassed = 1,
296}
297impl From<HSEBYP_A> for bool {
298    #[inline(always)]
299    fn from(variant: HSEBYP_A) -> Self {
300        variant as u8 != 0
301    }
302}
303impl HSEBYP_R {
304    ///Get enumerated values variant
305    #[inline(always)]
306    pub fn variant(&self) -> HSEBYP_A {
307        match self.bits {
308            false => HSEBYP_A::NotBypassed,
309            true => HSEBYP_A::Bypassed,
310        }
311    }
312    ///Checks if the value of the field is `NotBypassed`
313    #[inline(always)]
314    pub fn is_not_bypassed(&self) -> bool {
315        *self == HSEBYP_A::NotBypassed
316    }
317    ///Checks if the value of the field is `Bypassed`
318    #[inline(always)]
319    pub fn is_bypassed(&self) -> bool {
320        *self == HSEBYP_A::Bypassed
321    }
322}
323///Field `HSEBYP` writer - HSE crystal oscillator bypass
324pub type HSEBYP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, HSEBYP_A, O>;
325impl<'a, const O: u8> HSEBYP_W<'a, O> {
326    ///HSE oscillator not bypassed
327    #[inline(always)]
328    pub fn not_bypassed(self) -> &'a mut W {
329        self.variant(HSEBYP_A::NotBypassed)
330    }
331    ///HSE oscillator bypassed
332    #[inline(always)]
333    pub fn bypassed(self) -> &'a mut W {
334        self.variant(HSEBYP_A::Bypassed)
335    }
336}
337///Field `CSSON` reader - Clock security system enable
338pub use HSION_R as CSSON_R;
339///Field `CSSON` writer - Clock security system enable
340pub use HSION_W as CSSON_W;
341impl R {
342    ///Bit 8 - HSI16 clock enable
343    #[inline(always)]
344    pub fn hsion(&self) -> HSION_R {
345        HSION_R::new(((self.bits >> 8) & 1) != 0)
346    }
347    ///Bit 9 - HSI16 always enable for peripheral kernels
348    #[inline(always)]
349    pub fn hsikeron(&self) -> HSIKERON_R {
350        HSIKERON_R::new(((self.bits >> 9) & 1) != 0)
351    }
352    ///Bit 10 - HSI16 clock ready flag
353    #[inline(always)]
354    pub fn hsirdy(&self) -> HSIRDY_R {
355        HSIRDY_R::new(((self.bits >> 10) & 1) != 0)
356    }
357    ///Bits 11:13 - HSI16 clock division factor
358    #[inline(always)]
359    pub fn hsidiv(&self) -> HSIDIV_R {
360        HSIDIV_R::new(((self.bits >> 11) & 7) as u8)
361    }
362    ///Bit 16 - HSE clock enable
363    #[inline(always)]
364    pub fn hseon(&self) -> HSEON_R {
365        HSEON_R::new(((self.bits >> 16) & 1) != 0)
366    }
367    ///Bit 17 - HSE clock ready flag
368    #[inline(always)]
369    pub fn hserdy(&self) -> HSERDY_R {
370        HSERDY_R::new(((self.bits >> 17) & 1) != 0)
371    }
372    ///Bit 18 - HSE crystal oscillator bypass
373    #[inline(always)]
374    pub fn hsebyp(&self) -> HSEBYP_R {
375        HSEBYP_R::new(((self.bits >> 18) & 1) != 0)
376    }
377    ///Bit 19 - Clock security system enable
378    #[inline(always)]
379    pub fn csson(&self) -> CSSON_R {
380        CSSON_R::new(((self.bits >> 19) & 1) != 0)
381    }
382}
383impl W {
384    ///Bit 8 - HSI16 clock enable
385    #[inline(always)]
386    #[must_use]
387    pub fn hsion(&mut self) -> HSION_W<8> {
388        HSION_W::new(self)
389    }
390    ///Bit 9 - HSI16 always enable for peripheral kernels
391    #[inline(always)]
392    #[must_use]
393    pub fn hsikeron(&mut self) -> HSIKERON_W<9> {
394        HSIKERON_W::new(self)
395    }
396    ///Bit 10 - HSI16 clock ready flag
397    #[inline(always)]
398    #[must_use]
399    pub fn hsirdy(&mut self) -> HSIRDY_W<10> {
400        HSIRDY_W::new(self)
401    }
402    ///Bits 11:13 - HSI16 clock division factor
403    #[inline(always)]
404    #[must_use]
405    pub fn hsidiv(&mut self) -> HSIDIV_W<11> {
406        HSIDIV_W::new(self)
407    }
408    ///Bit 16 - HSE clock enable
409    #[inline(always)]
410    #[must_use]
411    pub fn hseon(&mut self) -> HSEON_W<16> {
412        HSEON_W::new(self)
413    }
414    ///Bit 17 - HSE clock ready flag
415    #[inline(always)]
416    #[must_use]
417    pub fn hserdy(&mut self) -> HSERDY_W<17> {
418        HSERDY_W::new(self)
419    }
420    ///Bit 18 - HSE crystal oscillator bypass
421    #[inline(always)]
422    #[must_use]
423    pub fn hsebyp(&mut self) -> HSEBYP_W<18> {
424        HSEBYP_W::new(self)
425    }
426    ///Bit 19 - Clock security system enable
427    #[inline(always)]
428    #[must_use]
429    pub fn csson(&mut self) -> CSSON_W<19> {
430        CSSON_W::new(self)
431    }
432    ///Writes raw bits to the register.
433    #[inline(always)]
434    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
435        self.0.bits(bits);
436        self
437    }
438}
439/**Clock control register
440
441This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
442
443For information about available fields see [cr](index.html) module*/
444pub struct CR_SPEC;
445impl crate::RegisterSpec for CR_SPEC {
446    type Ux = u32;
447}
448///`read()` method returns [cr::R](R) reader structure
449impl crate::Readable for CR_SPEC {
450    type Reader = R;
451}
452///`write(|w| ..)` method takes [cr::W](W) writer structure
453impl crate::Writable for CR_SPEC {
454    type Writer = W;
455    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
456    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
457}
458///`reset()` method sets CR to value 0x0100
459impl crate::Resettable for CR_SPEC {
460    const RESET_VALUE: Self::Ux = 0x0100;
461}
py32f0/py32f003/rcc/cr.rs

py32f0/py32f003/rcc/
cr.rs
