py32f0/py32f003/rcc/
apbrstr2.rs

1///Register `APBRSTR2` reader
2pub struct R(crate::R<APBRSTR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<APBRSTR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<APBRSTR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<APBRSTR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `APBRSTR2` writer
17pub struct W(crate::W<APBRSTR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<APBRSTR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<APBRSTR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<APBRSTR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `SYSCFGRST` reader - SYSCFG and COMP reset
38pub type SYSCFGRST_R = crate::BitReader<SYSCFGRSTW_A>;
39/**SYSCFG and COMP reset
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum SYSCFGRSTW_A {
44    ///1: Reset the module
45    Reset = 1,
46}
47impl From<SYSCFGRSTW_A> for bool {
48    #[inline(always)]
49    fn from(variant: SYSCFGRSTW_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl SYSCFGRST_R {
54    ///Get enumerated values variant
55    #[inline(always)]
56    pub fn variant(&self) -> Option<SYSCFGRSTW_A> {
57        match self.bits {
58            true => Some(SYSCFGRSTW_A::Reset),
59            _ => None,
60        }
61    }
62    ///Checks if the value of the field is `Reset`
63    #[inline(always)]
64    pub fn is_reset(&self) -> bool {
65        *self == SYSCFGRSTW_A::Reset
66    }
67}
68///Field `SYSCFGRST` writer - SYSCFG and COMP reset
69pub type SYSCFGRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, APBRSTR2_SPEC, SYSCFGRSTW_A, O>;
70impl<'a, const O: u8> SYSCFGRST_W<'a, O> {
71    ///Reset the module
72    #[inline(always)]
73    pub fn reset(self) -> &'a mut W {
74        self.variant(SYSCFGRSTW_A::Reset)
75    }
76}
77///Field `TIM1RST` reader - TIM1 timer reset
78pub use SYSCFGRST_R as TIM1RST_R;
79///Field `SPI1RST` reader - SPI1 reset
80pub use SYSCFGRST_R as SPI1RST_R;
81///Field `USART1RST` reader - USART1 reset
82pub use SYSCFGRST_R as USART1RST_R;
83///Field `TIM14RST` reader - TIM14 timer reset
84pub use SYSCFGRST_R as TIM14RST_R;
85///Field `TIM16RST` reader - TIM16 timer reset
86pub use SYSCFGRST_R as TIM16RST_R;
87///Field `TIM17RST` reader - TIM17 timer reset
88pub use SYSCFGRST_R as TIM17RST_R;
89///Field `ADCRST` reader - ADC reset
90pub use SYSCFGRST_R as ADCRST_R;
91///Field `COMP1RST` reader - COMP1 reset
92pub use SYSCFGRST_R as COMP1RST_R;
93///Field `COMP2RST` reader - COMP2 reset
94pub use SYSCFGRST_R as COMP2RST_R;
95///Field `TIM1RST` writer - TIM1 timer reset
96pub use SYSCFGRST_W as TIM1RST_W;
97///Field `SPI1RST` writer - SPI1 reset
98pub use SYSCFGRST_W as SPI1RST_W;
99///Field `USART1RST` writer - USART1 reset
100pub use SYSCFGRST_W as USART1RST_W;
101///Field `TIM14RST` writer - TIM14 timer reset
102pub use SYSCFGRST_W as TIM14RST_W;
103///Field `TIM16RST` writer - TIM16 timer reset
104pub use SYSCFGRST_W as TIM16RST_W;
105///Field `TIM17RST` writer - TIM17 timer reset
106pub use SYSCFGRST_W as TIM17RST_W;
107///Field `ADCRST` writer - ADC reset
108pub use SYSCFGRST_W as ADCRST_W;
109///Field `COMP1RST` writer - COMP1 reset
110pub use SYSCFGRST_W as COMP1RST_W;
111///Field `COMP2RST` writer - COMP2 reset
112pub use SYSCFGRST_W as COMP2RST_W;
113impl R {
114    ///Bit 0 - SYSCFG and COMP reset
115    #[inline(always)]
116    pub fn syscfgrst(&self) -> SYSCFGRST_R {
117        SYSCFGRST_R::new((self.bits & 1) != 0)
118    }
119    ///Bit 11 - TIM1 timer reset
120    #[inline(always)]
121    pub fn tim1rst(&self) -> TIM1RST_R {
122        TIM1RST_R::new(((self.bits >> 11) & 1) != 0)
123    }
124    ///Bit 12 - SPI1 reset
125    #[inline(always)]
126    pub fn spi1rst(&self) -> SPI1RST_R {
127        SPI1RST_R::new(((self.bits >> 12) & 1) != 0)
128    }
129    ///Bit 14 - USART1 reset
130    #[inline(always)]
131    pub fn usart1rst(&self) -> USART1RST_R {
132        USART1RST_R::new(((self.bits >> 14) & 1) != 0)
133    }
134    ///Bit 15 - TIM14 timer reset
135    #[inline(always)]
136    pub fn tim14rst(&self) -> TIM14RST_R {
137        TIM14RST_R::new(((self.bits >> 15) & 1) != 0)
138    }
139    ///Bit 17 - TIM16 timer reset
140    #[inline(always)]
141    pub fn tim16rst(&self) -> TIM16RST_R {
142        TIM16RST_R::new(((self.bits >> 17) & 1) != 0)
143    }
144    ///Bit 18 - TIM17 timer reset
145    #[inline(always)]
146    pub fn tim17rst(&self) -> TIM17RST_R {
147        TIM17RST_R::new(((self.bits >> 18) & 1) != 0)
148    }
149    ///Bit 20 - ADC reset
150    #[inline(always)]
151    pub fn adcrst(&self) -> ADCRST_R {
152        ADCRST_R::new(((self.bits >> 20) & 1) != 0)
153    }
154    ///Bit 21 - COMP1 reset
155    #[inline(always)]
156    pub fn comp1rst(&self) -> COMP1RST_R {
157        COMP1RST_R::new(((self.bits >> 21) & 1) != 0)
158    }
159    ///Bit 22 - COMP2 reset
160    #[inline(always)]
161    pub fn comp2rst(&self) -> COMP2RST_R {
162        COMP2RST_R::new(((self.bits >> 22) & 1) != 0)
163    }
164}
165impl W {
166    ///Bit 0 - SYSCFG and COMP reset
167    #[inline(always)]
168    #[must_use]
169    pub fn syscfgrst(&mut self) -> SYSCFGRST_W<0> {
170        SYSCFGRST_W::new(self)
171    }
172    ///Bit 11 - TIM1 timer reset
173    #[inline(always)]
174    #[must_use]
175    pub fn tim1rst(&mut self) -> TIM1RST_W<11> {
176        TIM1RST_W::new(self)
177    }
178    ///Bit 12 - SPI1 reset
179    #[inline(always)]
180    #[must_use]
181    pub fn spi1rst(&mut self) -> SPI1RST_W<12> {
182        SPI1RST_W::new(self)
183    }
184    ///Bit 14 - USART1 reset
185    #[inline(always)]
186    #[must_use]
187    pub fn usart1rst(&mut self) -> USART1RST_W<14> {
188        USART1RST_W::new(self)
189    }
190    ///Bit 15 - TIM14 timer reset
191    #[inline(always)]
192    #[must_use]
193    pub fn tim14rst(&mut self) -> TIM14RST_W<15> {
194        TIM14RST_W::new(self)
195    }
196    ///Bit 17 - TIM16 timer reset
197    #[inline(always)]
198    #[must_use]
199    pub fn tim16rst(&mut self) -> TIM16RST_W<17> {
200        TIM16RST_W::new(self)
201    }
202    ///Bit 18 - TIM17 timer reset
203    #[inline(always)]
204    #[must_use]
205    pub fn tim17rst(&mut self) -> TIM17RST_W<18> {
206        TIM17RST_W::new(self)
207    }
208    ///Bit 20 - ADC reset
209    #[inline(always)]
210    #[must_use]
211    pub fn adcrst(&mut self) -> ADCRST_W<20> {
212        ADCRST_W::new(self)
213    }
214    ///Bit 21 - COMP1 reset
215    #[inline(always)]
216    #[must_use]
217    pub fn comp1rst(&mut self) -> COMP1RST_W<21> {
218        COMP1RST_W::new(self)
219    }
220    ///Bit 22 - COMP2 reset
221    #[inline(always)]
222    #[must_use]
223    pub fn comp2rst(&mut self) -> COMP2RST_W<22> {
224        COMP2RST_W::new(self)
225    }
226    ///Writes raw bits to the register.
227    #[inline(always)]
228    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
229        self.0.bits(bits);
230        self
231    }
232}
233/**APB peripheral reset register 2
234
235This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
236
237For information about available fields see [apbrstr2](index.html) module*/
238pub struct APBRSTR2_SPEC;
239impl crate::RegisterSpec for APBRSTR2_SPEC {
240    type Ux = u32;
241}
242///`read()` method returns [apbrstr2::R](R) reader structure
243impl crate::Readable for APBRSTR2_SPEC {
244    type Reader = R;
245}
246///`write(|w| ..)` method takes [apbrstr2::W](W) writer structure
247impl crate::Writable for APBRSTR2_SPEC {
248    type Writer = W;
249    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
250    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
251}
252///`reset()` method sets APBRSTR2 to value 0
253impl crate::Resettable for APBRSTR2_SPEC {
254    const RESET_VALUE: Self::Ux = 0;
255}
py32f0/py32f003/rcc/apbrstr2.rs

py32f0/py32f003/rcc/
apbrstr2.rs
