py32f0/py32f003/pwr/
cr2.rs

1///Register `CR2` reader
2pub struct R(crate::R<CR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR2` writer
17pub struct W(crate::W<CR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `PVDE` reader - Power voltage detector enable
38pub type PVDE_R = crate::BitReader<PVDE_A>;
39/**Power voltage detector enable
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum PVDE_A {
44    ///0: PVD Disabled
45    Disabled = 0,
46    ///1: PVD Enabled
47    Enabled = 1,
48}
49impl From<PVDE_A> for bool {
50    #[inline(always)]
51    fn from(variant: PVDE_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl PVDE_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> PVDE_A {
59        match self.bits {
60            false => PVDE_A::Disabled,
61            true => PVDE_A::Enabled,
62        }
63    }
64    ///Checks if the value of the field is `Disabled`
65    #[inline(always)]
66    pub fn is_disabled(&self) -> bool {
67        *self == PVDE_A::Disabled
68    }
69    ///Checks if the value of the field is `Enabled`
70    #[inline(always)]
71    pub fn is_enabled(&self) -> bool {
72        *self == PVDE_A::Enabled
73    }
74}
75///Field `PVDE` writer - Power voltage detector enable
76pub type PVDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, PVDE_A, O>;
77impl<'a, const O: u8> PVDE_W<'a, O> {
78    ///PVD Disabled
79    #[inline(always)]
80    pub fn disabled(self) -> &'a mut W {
81        self.variant(PVDE_A::Disabled)
82    }
83    ///PVD Enabled
84    #[inline(always)]
85    pub fn enabled(self) -> &'a mut W {
86        self.variant(PVDE_A::Enabled)
87    }
88}
89///Field `PVD_SRCSEL` reader - Power voltage detector volatage selection
90pub type PVD_SRCSEL_R = crate::BitReader<PVD_SRCSEL_A>;
91/**Power voltage detector volatage selection
92
93Value on reset: 0*/
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum PVD_SRCSEL_A {
96    ///0: VCC as detector source
97    Vcc = 0,
98    ///1: PB7 pin as detector source
99    Pb7 = 1,
100}
101impl From<PVD_SRCSEL_A> for bool {
102    #[inline(always)]
103    fn from(variant: PVD_SRCSEL_A) -> Self {
104        variant as u8 != 0
105    }
106}
107impl PVD_SRCSEL_R {
108    ///Get enumerated values variant
109    #[inline(always)]
110    pub fn variant(&self) -> PVD_SRCSEL_A {
111        match self.bits {
112            false => PVD_SRCSEL_A::Vcc,
113            true => PVD_SRCSEL_A::Pb7,
114        }
115    }
116    ///Checks if the value of the field is `Vcc`
117    #[inline(always)]
118    pub fn is_vcc(&self) -> bool {
119        *self == PVD_SRCSEL_A::Vcc
120    }
121    ///Checks if the value of the field is `Pb7`
122    #[inline(always)]
123    pub fn is_pb7(&self) -> bool {
124        *self == PVD_SRCSEL_A::Pb7
125    }
126}
127///Field `PVD_SRCSEL` writer - Power voltage detector volatage selection
128pub type PVD_SRCSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, PVD_SRCSEL_A, O>;
129impl<'a, const O: u8> PVD_SRCSEL_W<'a, O> {
130    ///VCC as detector source
131    #[inline(always)]
132    pub fn vcc(self) -> &'a mut W {
133        self.variant(PVD_SRCSEL_A::Vcc)
134    }
135    ///PB7 pin as detector source
136    #[inline(always)]
137    pub fn pb7(self) -> &'a mut W {
138        self.variant(PVD_SRCSEL_A::Pb7)
139    }
140}
141///Field `PVDT` reader - Power voltage detector threshold selection
142pub type PVDT_R = crate::FieldReader<u8, PVDT_A>;
143/**Power voltage detector threshold selection
144
145Value on reset: 0*/
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147#[repr(u8)]
148pub enum PVDT_A {
149    ///0: 1.8 V
150    V18 = 0,
151    ///1: 2.0 V
152    V20 = 1,
153    ///2: 2.2 V
154    V22 = 2,
155    ///3: 2.4 V
156    V24 = 3,
157    ///4: 2.6 V
158    V26 = 4,
159    ///5: 2.8 V
160    V28 = 5,
161    ///6: 3.0 V
162    V30 = 6,
163    ///7: 3.2 V
164    V32 = 7,
165}
166impl From<PVDT_A> for u8 {
167    #[inline(always)]
168    fn from(variant: PVDT_A) -> Self {
169        variant as _
170    }
171}
172impl PVDT_R {
173    ///Get enumerated values variant
174    #[inline(always)]
175    pub fn variant(&self) -> PVDT_A {
176        match self.bits {
177            0 => PVDT_A::V18,
178            1 => PVDT_A::V20,
179            2 => PVDT_A::V22,
180            3 => PVDT_A::V24,
181            4 => PVDT_A::V26,
182            5 => PVDT_A::V28,
183            6 => PVDT_A::V30,
184            7 => PVDT_A::V32,
185            _ => unreachable!(),
186        }
187    }
188    ///Checks if the value of the field is `V18`
189    #[inline(always)]
190    pub fn is_v1_8(&self) -> bool {
191        *self == PVDT_A::V18
192    }
193    ///Checks if the value of the field is `V20`
194    #[inline(always)]
195    pub fn is_v2_0(&self) -> bool {
196        *self == PVDT_A::V20
197    }
198    ///Checks if the value of the field is `V22`
199    #[inline(always)]
200    pub fn is_v2_2(&self) -> bool {
201        *self == PVDT_A::V22
202    }
203    ///Checks if the value of the field is `V24`
204    #[inline(always)]
205    pub fn is_v2_4(&self) -> bool {
206        *self == PVDT_A::V24
207    }
208    ///Checks if the value of the field is `V26`
209    #[inline(always)]
210    pub fn is_v2_6(&self) -> bool {
211        *self == PVDT_A::V26
212    }
213    ///Checks if the value of the field is `V28`
214    #[inline(always)]
215    pub fn is_v2_8(&self) -> bool {
216        *self == PVDT_A::V28
217    }
218    ///Checks if the value of the field is `V30`
219    #[inline(always)]
220    pub fn is_v3_0(&self) -> bool {
221        *self == PVDT_A::V30
222    }
223    ///Checks if the value of the field is `V32`
224    #[inline(always)]
225    pub fn is_v3_2(&self) -> bool {
226        *self == PVDT_A::V32
227    }
228}
229///Field `PVDT` writer - Power voltage detector threshold selection
230pub type PVDT_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, PVDT_A, 3, O>;
231impl<'a, const O: u8> PVDT_W<'a, O> {
232    ///1.8 V
233    #[inline(always)]
234    pub fn v1_8(self) -> &'a mut W {
235        self.variant(PVDT_A::V18)
236    }
237    ///2.0 V
238    #[inline(always)]
239    pub fn v2_0(self) -> &'a mut W {
240        self.variant(PVDT_A::V20)
241    }
242    ///2.2 V
243    #[inline(always)]
244    pub fn v2_2(self) -> &'a mut W {
245        self.variant(PVDT_A::V22)
246    }
247    ///2.4 V
248    #[inline(always)]
249    pub fn v2_4(self) -> &'a mut W {
250        self.variant(PVDT_A::V24)
251    }
252    ///2.6 V
253    #[inline(always)]
254    pub fn v2_6(self) -> &'a mut W {
255        self.variant(PVDT_A::V26)
256    }
257    ///2.8 V
258    #[inline(always)]
259    pub fn v2_8(self) -> &'a mut W {
260        self.variant(PVDT_A::V28)
261    }
262    ///3.0 V
263    #[inline(always)]
264    pub fn v3_0(self) -> &'a mut W {
265        self.variant(PVDT_A::V30)
266    }
267    ///3.2 V
268    #[inline(always)]
269    pub fn v3_2(self) -> &'a mut W {
270        self.variant(PVDT_A::V32)
271    }
272}
273///Field `FLTEN` reader - Digital filter enable
274pub type FLTEN_R = crate::BitReader<FLTEN_A>;
275/**Digital filter enable
276
277Value on reset: 1*/
278#[derive(Clone, Copy, Debug, PartialEq, Eq)]
279pub enum FLTEN_A {
280    ///0: Digital filter disabled
281    Disabled = 0,
282    ///1: Digital filter enabled
283    Enabled = 1,
284}
285impl From<FLTEN_A> for bool {
286    #[inline(always)]
287    fn from(variant: FLTEN_A) -> Self {
288        variant as u8 != 0
289    }
290}
291impl FLTEN_R {
292    ///Get enumerated values variant
293    #[inline(always)]
294    pub fn variant(&self) -> FLTEN_A {
295        match self.bits {
296            false => FLTEN_A::Disabled,
297            true => FLTEN_A::Enabled,
298        }
299    }
300    ///Checks if the value of the field is `Disabled`
301    #[inline(always)]
302    pub fn is_disabled(&self) -> bool {
303        *self == FLTEN_A::Disabled
304    }
305    ///Checks if the value of the field is `Enabled`
306    #[inline(always)]
307    pub fn is_enabled(&self) -> bool {
308        *self == FLTEN_A::Enabled
309    }
310}
311///Field `FLTEN` writer - Digital filter enable
312pub type FLTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, FLTEN_A, O>;
313impl<'a, const O: u8> FLTEN_W<'a, O> {
314    ///Digital filter disabled
315    #[inline(always)]
316    pub fn disabled(self) -> &'a mut W {
317        self.variant(FLTEN_A::Disabled)
318    }
319    ///Digital filter enabled
320    #[inline(always)]
321    pub fn enabled(self) -> &'a mut W {
322        self.variant(FLTEN_A::Enabled)
323    }
324}
325///Field `FLT_TIME` reader - Digital filter time configuration
326pub type FLT_TIME_R = crate::FieldReader<u8, FLT_TIME_A>;
327/**Digital filter time configuration
328
329Value on reset: 2*/
330#[derive(Clone, Copy, Debug, PartialEq, Eq)]
331#[repr(u8)]
332pub enum FLT_TIME_A {
333    ///0: Filter time is about 30 us
334    T30us = 0,
335    ///1: Filter time is about 60 us
336    T60us = 1,
337    ///2: Filter time is about 120 us
338    T120us = 2,
339    ///3: Filter time is about 480 us
340    T480us = 3,
341    ///4: Filter time is about 1.92 ms
342    T192ms = 4,
343    ///5: Filter time is about 3.8 ms
344    T38ms = 5,
345    ///6: Filter time is about 30.7 ms
346    T307ms = 6,
347}
348impl From<FLT_TIME_A> for u8 {
349    #[inline(always)]
350    fn from(variant: FLT_TIME_A) -> Self {
351        variant as _
352    }
353}
354impl FLT_TIME_R {
355    ///Get enumerated values variant
356    #[inline(always)]
357    pub fn variant(&self) -> Option<FLT_TIME_A> {
358        match self.bits {
359            0 => Some(FLT_TIME_A::T30us),
360            1 => Some(FLT_TIME_A::T60us),
361            2 => Some(FLT_TIME_A::T120us),
362            3 => Some(FLT_TIME_A::T480us),
363            4 => Some(FLT_TIME_A::T192ms),
364            5 => Some(FLT_TIME_A::T38ms),
365            6 => Some(FLT_TIME_A::T307ms),
366            _ => None,
367        }
368    }
369    ///Checks if the value of the field is `T30us`
370    #[inline(always)]
371    pub fn is_t30us(&self) -> bool {
372        *self == FLT_TIME_A::T30us
373    }
374    ///Checks if the value of the field is `T60us`
375    #[inline(always)]
376    pub fn is_t60us(&self) -> bool {
377        *self == FLT_TIME_A::T60us
378    }
379    ///Checks if the value of the field is `T120us`
380    #[inline(always)]
381    pub fn is_t120us(&self) -> bool {
382        *self == FLT_TIME_A::T120us
383    }
384    ///Checks if the value of the field is `T480us`
385    #[inline(always)]
386    pub fn is_t480us(&self) -> bool {
387        *self == FLT_TIME_A::T480us
388    }
389    ///Checks if the value of the field is `T192ms`
390    #[inline(always)]
391    pub fn is_t1_92ms(&self) -> bool {
392        *self == FLT_TIME_A::T192ms
393    }
394    ///Checks if the value of the field is `T38ms`
395    #[inline(always)]
396    pub fn is_t3_8ms(&self) -> bool {
397        *self == FLT_TIME_A::T38ms
398    }
399    ///Checks if the value of the field is `T307ms`
400    #[inline(always)]
401    pub fn is_t30_7ms(&self) -> bool {
402        *self == FLT_TIME_A::T307ms
403    }
404}
405///Field `FLT_TIME` writer - Digital filter time configuration
406pub type FLT_TIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR2_SPEC, u8, FLT_TIME_A, 3, O>;
407impl<'a, const O: u8> FLT_TIME_W<'a, O> {
408    ///Filter time is about 30 us
409    #[inline(always)]
410    pub fn t30us(self) -> &'a mut W {
411        self.variant(FLT_TIME_A::T30us)
412    }
413    ///Filter time is about 60 us
414    #[inline(always)]
415    pub fn t60us(self) -> &'a mut W {
416        self.variant(FLT_TIME_A::T60us)
417    }
418    ///Filter time is about 120 us
419    #[inline(always)]
420    pub fn t120us(self) -> &'a mut W {
421        self.variant(FLT_TIME_A::T120us)
422    }
423    ///Filter time is about 480 us
424    #[inline(always)]
425    pub fn t480us(self) -> &'a mut W {
426        self.variant(FLT_TIME_A::T480us)
427    }
428    ///Filter time is about 1.92 ms
429    #[inline(always)]
430    pub fn t1_92ms(self) -> &'a mut W {
431        self.variant(FLT_TIME_A::T192ms)
432    }
433    ///Filter time is about 3.8 ms
434    #[inline(always)]
435    pub fn t3_8ms(self) -> &'a mut W {
436        self.variant(FLT_TIME_A::T38ms)
437    }
438    ///Filter time is about 30.7 ms
439    #[inline(always)]
440    pub fn t30_7ms(self) -> &'a mut W {
441        self.variant(FLT_TIME_A::T307ms)
442    }
443}
444impl R {
445    ///Bit 0 - Power voltage detector enable
446    #[inline(always)]
447    pub fn pvde(&self) -> PVDE_R {
448        PVDE_R::new((self.bits & 1) != 0)
449    }
450    ///Bit 2 - Power voltage detector volatage selection
451    #[inline(always)]
452    pub fn pvd_srcsel(&self) -> PVD_SRCSEL_R {
453        PVD_SRCSEL_R::new(((self.bits >> 2) & 1) != 0)
454    }
455    ///Bits 4:6 - Power voltage detector threshold selection
456    #[inline(always)]
457    pub fn pvdt(&self) -> PVDT_R {
458        PVDT_R::new(((self.bits >> 4) & 7) as u8)
459    }
460    ///Bit 8 - Digital filter enable
461    #[inline(always)]
462    pub fn flten(&self) -> FLTEN_R {
463        FLTEN_R::new(((self.bits >> 8) & 1) != 0)
464    }
465    ///Bits 9:11 - Digital filter time configuration
466    #[inline(always)]
467    pub fn flt_time(&self) -> FLT_TIME_R {
468        FLT_TIME_R::new(((self.bits >> 9) & 7) as u8)
469    }
470}
471impl W {
472    ///Bit 0 - Power voltage detector enable
473    #[inline(always)]
474    #[must_use]
475    pub fn pvde(&mut self) -> PVDE_W<0> {
476        PVDE_W::new(self)
477    }
478    ///Bit 2 - Power voltage detector volatage selection
479    #[inline(always)]
480    #[must_use]
481    pub fn pvd_srcsel(&mut self) -> PVD_SRCSEL_W<2> {
482        PVD_SRCSEL_W::new(self)
483    }
484    ///Bits 4:6 - Power voltage detector threshold selection
485    #[inline(always)]
486    #[must_use]
487    pub fn pvdt(&mut self) -> PVDT_W<4> {
488        PVDT_W::new(self)
489    }
490    ///Bit 8 - Digital filter enable
491    #[inline(always)]
492    #[must_use]
493    pub fn flten(&mut self) -> FLTEN_W<8> {
494        FLTEN_W::new(self)
495    }
496    ///Bits 9:11 - Digital filter time configuration
497    #[inline(always)]
498    #[must_use]
499    pub fn flt_time(&mut self) -> FLT_TIME_W<9> {
500        FLT_TIME_W::new(self)
501    }
502    ///Writes raw bits to the register.
503    #[inline(always)]
504    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
505        self.0.bits(bits);
506        self
507    }
508}
509/**Power control register 2
510
511This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
512
513For information about available fields see [cr2](index.html) module*/
514pub struct CR2_SPEC;
515impl crate::RegisterSpec for CR2_SPEC {
516    type Ux = u32;
517}
518///`read()` method returns [cr2::R](R) reader structure
519impl crate::Readable for CR2_SPEC {
520    type Reader = R;
521}
522///`write(|w| ..)` method takes [cr2::W](W) writer structure
523impl crate::Writable for CR2_SPEC {
524    type Writer = W;
525    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
526    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
527}
528///`reset()` method sets CR2 to value 0x0500
529impl crate::Resettable for CR2_SPEC {
530    const RESET_VALUE: Self::Ux = 0x0500;
531}
py32f0/py32f003/pwr/cr2.rs

py32f0/py32f003/pwr/
cr2.rs
