py32f0/py32f003/lptim/
ier.rs

1///Register `IER` reader
2pub struct R(crate::R<IER_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IER_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IER_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `IER` writer
17pub struct W(crate::W<IER_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<IER_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<IER_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<IER_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `ARRMIE` reader - Autoreload match Interrupt Enable
38pub type ARRMIE_R = crate::BitReader<ARRMIE_A>;
39/**Autoreload match Interrupt Enable
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum ARRMIE_A {
44    ///0: ARRM interrupt disabled
45    Disabled = 0,
46    ///1: ARRM interrupt enabled
47    Enabled = 1,
48}
49impl From<ARRMIE_A> for bool {
50    #[inline(always)]
51    fn from(variant: ARRMIE_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl ARRMIE_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> ARRMIE_A {
59        match self.bits {
60            false => ARRMIE_A::Disabled,
61            true => ARRMIE_A::Enabled,
62        }
63    }
64    ///Checks if the value of the field is `Disabled`
65    #[inline(always)]
66    pub fn is_disabled(&self) -> bool {
67        *self == ARRMIE_A::Disabled
68    }
69    ///Checks if the value of the field is `Enabled`
70    #[inline(always)]
71    pub fn is_enabled(&self) -> bool {
72        *self == ARRMIE_A::Enabled
73    }
74}
75///Field `ARRMIE` writer - Autoreload match Interrupt Enable
76pub type ARRMIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IER_SPEC, ARRMIE_A, O>;
77impl<'a, const O: u8> ARRMIE_W<'a, O> {
78    ///ARRM interrupt disabled
79    #[inline(always)]
80    pub fn disabled(self) -> &'a mut W {
81        self.variant(ARRMIE_A::Disabled)
82    }
83    ///ARRM interrupt enabled
84    #[inline(always)]
85    pub fn enabled(self) -> &'a mut W {
86        self.variant(ARRMIE_A::Enabled)
87    }
88}
89impl R {
90    ///Bit 1 - Autoreload match Interrupt Enable
91    #[inline(always)]
92    pub fn arrmie(&self) -> ARRMIE_R {
93        ARRMIE_R::new(((self.bits >> 1) & 1) != 0)
94    }
95}
96impl W {
97    ///Bit 1 - Autoreload match Interrupt Enable
98    #[inline(always)]
99    #[must_use]
100    pub fn arrmie(&mut self) -> ARRMIE_W<1> {
101        ARRMIE_W::new(self)
102    }
103    ///Writes raw bits to the register.
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110/**Interrupt Enable Register
111
112This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
113
114For information about available fields see [ier](index.html) module*/
115pub struct IER_SPEC;
116impl crate::RegisterSpec for IER_SPEC {
117    type Ux = u32;
118}
119///`read()` method returns [ier::R](R) reader structure
120impl crate::Readable for IER_SPEC {
121    type Reader = R;
122}
123///`write(|w| ..)` method takes [ier::W](W) writer structure
124impl crate::Writable for IER_SPEC {
125    type Writer = W;
126    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
127    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
128}
129///`reset()` method sets IER to value 0
130impl crate::Resettable for IER_SPEC {
131    const RESET_VALUE: Self::Ux = 0;
132}
py32f0/py32f003/lptim/ier.rs

py32f0/py32f003/lptim/
ier.rs
