py32f0/py32f003/dma/
ifcr.rs

1///Register `IFCR` writer
2pub struct W(crate::W<IFCR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IFCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IFCR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IFCR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22/**Channel %s Global interrupt clear
23
24Value on reset: 0*/
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum CGIF1_AW {
27    ///1: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
28    Clear = 1,
29}
30impl From<CGIF1_AW> for bool {
31    #[inline(always)]
32    fn from(variant: CGIF1_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36///Field `CGIF[1-3]` writer - Channel %s Global interrupt clear
37pub type CGIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, CGIF1_AW, O>;
38impl<'a, const O: u8> CGIF_W<'a, O> {
39    ///Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register
40    #[inline(always)]
41    pub fn clear(self) -> &'a mut W {
42        self.variant(CGIF1_AW::Clear)
43    }
44}
45/**Channel %s Transfer Complete clear
46
47Value on reset: 0*/
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49pub enum CTCIF1_AW {
50    ///1: Clears the TCIF flag in the ISR register
51    Clear = 1,
52}
53impl From<CTCIF1_AW> for bool {
54    #[inline(always)]
55    fn from(variant: CTCIF1_AW) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `CTCIF[1-3]` writer - Channel %s Transfer Complete clear
60pub type CTCIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, CTCIF1_AW, O>;
61impl<'a, const O: u8> CTCIF_W<'a, O> {
62    ///Clears the TCIF flag in the ISR register
63    #[inline(always)]
64    pub fn clear(self) -> &'a mut W {
65        self.variant(CTCIF1_AW::Clear)
66    }
67}
68/**Channel %s Half Transfer clear
69
70Value on reset: 0*/
71#[derive(Clone, Copy, Debug, PartialEq, Eq)]
72pub enum CHTIF1_AW {
73    ///1: Clears the HTIF flag in the ISR register
74    Clear = 1,
75}
76impl From<CHTIF1_AW> for bool {
77    #[inline(always)]
78    fn from(variant: CHTIF1_AW) -> Self {
79        variant as u8 != 0
80    }
81}
82///Field `CHTIF[1-3]` writer - Channel %s Half Transfer clear
83pub type CHTIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, CHTIF1_AW, O>;
84impl<'a, const O: u8> CHTIF_W<'a, O> {
85    ///Clears the HTIF flag in the ISR register
86    #[inline(always)]
87    pub fn clear(self) -> &'a mut W {
88        self.variant(CHTIF1_AW::Clear)
89    }
90}
91/**Channel %s Transfer Error clear
92
93Value on reset: 0*/
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum CTEIF1_AW {
96    ///1: Clears the TEIF flag in the ISR register
97    Clear = 1,
98}
99impl From<CTEIF1_AW> for bool {
100    #[inline(always)]
101    fn from(variant: CTEIF1_AW) -> Self {
102        variant as u8 != 0
103    }
104}
105///Field `CTEIF[1-3]` writer - Channel %s Transfer Error clear
106pub type CTEIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCR_SPEC, CTEIF1_AW, O>;
107impl<'a, const O: u8> CTEIF_W<'a, O> {
108    ///Clears the TEIF flag in the ISR register
109    #[inline(always)]
110    pub fn clear(self) -> &'a mut W {
111        self.variant(CTEIF1_AW::Clear)
112    }
113}
114impl W {
115    /**Channel [1-3]
116    Global interrupt clear*/
117    #[inline(always)]
118    #[must_use]
119    pub unsafe fn cgif<const O: u8>(&mut self) -> CGIF_W<O> {
120        CGIF_W::new(self)
121    }
122    ///Bit 0 - Channel 1 Global interrupt clear
123    #[inline(always)]
124    #[must_use]
125    pub fn cgif1(&mut self) -> CGIF_W<0> {
126        CGIF_W::new(self)
127    }
128    ///Bit 4 - Channel 2 Global interrupt clear
129    #[inline(always)]
130    #[must_use]
131    pub fn cgif2(&mut self) -> CGIF_W<4> {
132        CGIF_W::new(self)
133    }
134    ///Bit 8 - Channel 3 Global interrupt clear
135    #[inline(always)]
136    #[must_use]
137    pub fn cgif3(&mut self) -> CGIF_W<8> {
138        CGIF_W::new(self)
139    }
140    /**Channel [1-3]
141    Transfer Complete clear*/
142    #[inline(always)]
143    #[must_use]
144    pub unsafe fn ctcif<const O: u8>(&mut self) -> CTCIF_W<O> {
145        CTCIF_W::new(self)
146    }
147    ///Bit 1 - Channel 1 Transfer Complete clear
148    #[inline(always)]
149    #[must_use]
150    pub fn ctcif1(&mut self) -> CTCIF_W<1> {
151        CTCIF_W::new(self)
152    }
153    ///Bit 5 - Channel 2 Transfer Complete clear
154    #[inline(always)]
155    #[must_use]
156    pub fn ctcif2(&mut self) -> CTCIF_W<5> {
157        CTCIF_W::new(self)
158    }
159    ///Bit 9 - Channel 3 Transfer Complete clear
160    #[inline(always)]
161    #[must_use]
162    pub fn ctcif3(&mut self) -> CTCIF_W<9> {
163        CTCIF_W::new(self)
164    }
165    /**Channel [1-3]
166    Half Transfer clear*/
167    #[inline(always)]
168    #[must_use]
169    pub unsafe fn chtif<const O: u8>(&mut self) -> CHTIF_W<O> {
170        CHTIF_W::new(self)
171    }
172    ///Bit 2 - Channel 1 Half Transfer clear
173    #[inline(always)]
174    #[must_use]
175    pub fn chtif1(&mut self) -> CHTIF_W<2> {
176        CHTIF_W::new(self)
177    }
178    ///Bit 6 - Channel 2 Half Transfer clear
179    #[inline(always)]
180    #[must_use]
181    pub fn chtif2(&mut self) -> CHTIF_W<6> {
182        CHTIF_W::new(self)
183    }
184    ///Bit 10 - Channel 3 Half Transfer clear
185    #[inline(always)]
186    #[must_use]
187    pub fn chtif3(&mut self) -> CHTIF_W<10> {
188        CHTIF_W::new(self)
189    }
190    /**Channel [1-3]
191    Transfer Error clear*/
192    #[inline(always)]
193    #[must_use]
194    pub unsafe fn cteif<const O: u8>(&mut self) -> CTEIF_W<O> {
195        CTEIF_W::new(self)
196    }
197    ///Bit 3 - Channel 1 Transfer Error clear
198    #[inline(always)]
199    #[must_use]
200    pub fn cteif1(&mut self) -> CTEIF_W<3> {
201        CTEIF_W::new(self)
202    }
203    ///Bit 7 - Channel 2 Transfer Error clear
204    #[inline(always)]
205    #[must_use]
206    pub fn cteif2(&mut self) -> CTEIF_W<7> {
207        CTEIF_W::new(self)
208    }
209    ///Bit 11 - Channel 3 Transfer Error clear
210    #[inline(always)]
211    #[must_use]
212    pub fn cteif3(&mut self) -> CTEIF_W<11> {
213        CTEIF_W::new(self)
214    }
215    ///Writes raw bits to the register.
216    #[inline(always)]
217    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
218        self.0.bits(bits);
219        self
220    }
221}
222/**DMA interrupt flag clear register (DMA_IFCR)
223
224This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
225
226For information about available fields see [ifcr](index.html) module*/
227pub struct IFCR_SPEC;
228impl crate::RegisterSpec for IFCR_SPEC {
229    type Ux = u32;
230}
231///`write(|w| ..)` method takes [ifcr::W](W) writer structure
232impl crate::Writable for IFCR_SPEC {
233    type Writer = W;
234    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
235    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
236}
237///`reset()` method sets IFCR to value 0
238impl crate::Resettable for IFCR_SPEC {
239    const RESET_VALUE: Self::Ux = 0;
240}
py32f0/py32f003/dma/ifcr.rs

py32f0/py32f003/dma/
ifcr.rs
