py32f0/py32f003/dma/ch/
cr.rs

1///Register `CR` reader
2pub struct R(crate::R<CR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR` writer
17pub struct W(crate::W<CR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `EN` reader - Channel enable
38pub type EN_R = crate::BitReader<EN_A>;
39/**Channel enable
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum EN_A {
44    ///0: Channel disabled
45    Disabled = 0,
46    ///1: Channel enabled
47    Enabled = 1,
48}
49impl From<EN_A> for bool {
50    #[inline(always)]
51    fn from(variant: EN_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl EN_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> EN_A {
59        match self.bits {
60            false => EN_A::Disabled,
61            true => EN_A::Enabled,
62        }
63    }
64    ///Checks if the value of the field is `Disabled`
65    #[inline(always)]
66    pub fn is_disabled(&self) -> bool {
67        *self == EN_A::Disabled
68    }
69    ///Checks if the value of the field is `Enabled`
70    #[inline(always)]
71    pub fn is_enabled(&self) -> bool {
72        *self == EN_A::Enabled
73    }
74}
75///Field `EN` writer - Channel enable
76pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, EN_A, O>;
77impl<'a, const O: u8> EN_W<'a, O> {
78    ///Channel disabled
79    #[inline(always)]
80    pub fn disabled(self) -> &'a mut W {
81        self.variant(EN_A::Disabled)
82    }
83    ///Channel enabled
84    #[inline(always)]
85    pub fn enabled(self) -> &'a mut W {
86        self.variant(EN_A::Enabled)
87    }
88}
89///Field `TCIE` reader - Transfer complete interrupt enable
90pub type TCIE_R = crate::BitReader<TCIE_A>;
91/**Transfer complete interrupt enable
92
93Value on reset: 0*/
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum TCIE_A {
96    ///0: Transfer Complete interrupt disabled
97    Disabled = 0,
98    ///1: Transfer Complete interrupt enabled
99    Enabled = 1,
100}
101impl From<TCIE_A> for bool {
102    #[inline(always)]
103    fn from(variant: TCIE_A) -> Self {
104        variant as u8 != 0
105    }
106}
107impl TCIE_R {
108    ///Get enumerated values variant
109    #[inline(always)]
110    pub fn variant(&self) -> TCIE_A {
111        match self.bits {
112            false => TCIE_A::Disabled,
113            true => TCIE_A::Enabled,
114        }
115    }
116    ///Checks if the value of the field is `Disabled`
117    #[inline(always)]
118    pub fn is_disabled(&self) -> bool {
119        *self == TCIE_A::Disabled
120    }
121    ///Checks if the value of the field is `Enabled`
122    #[inline(always)]
123    pub fn is_enabled(&self) -> bool {
124        *self == TCIE_A::Enabled
125    }
126}
127///Field `TCIE` writer - Transfer complete interrupt enable
128pub type TCIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, TCIE_A, O>;
129impl<'a, const O: u8> TCIE_W<'a, O> {
130    ///Transfer Complete interrupt disabled
131    #[inline(always)]
132    pub fn disabled(self) -> &'a mut W {
133        self.variant(TCIE_A::Disabled)
134    }
135    ///Transfer Complete interrupt enabled
136    #[inline(always)]
137    pub fn enabled(self) -> &'a mut W {
138        self.variant(TCIE_A::Enabled)
139    }
140}
141///Field `HTIE` reader - Half Transfer interrupt enable
142pub type HTIE_R = crate::BitReader<HTIE_A>;
143/**Half Transfer interrupt enable
144
145Value on reset: 0*/
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum HTIE_A {
148    ///0: Half Transfer interrupt disabled
149    Disabled = 0,
150    ///1: Half Transfer interrupt enabled
151    Enabled = 1,
152}
153impl From<HTIE_A> for bool {
154    #[inline(always)]
155    fn from(variant: HTIE_A) -> Self {
156        variant as u8 != 0
157    }
158}
159impl HTIE_R {
160    ///Get enumerated values variant
161    #[inline(always)]
162    pub fn variant(&self) -> HTIE_A {
163        match self.bits {
164            false => HTIE_A::Disabled,
165            true => HTIE_A::Enabled,
166        }
167    }
168    ///Checks if the value of the field is `Disabled`
169    #[inline(always)]
170    pub fn is_disabled(&self) -> bool {
171        *self == HTIE_A::Disabled
172    }
173    ///Checks if the value of the field is `Enabled`
174    #[inline(always)]
175    pub fn is_enabled(&self) -> bool {
176        *self == HTIE_A::Enabled
177    }
178}
179///Field `HTIE` writer - Half Transfer interrupt enable
180pub type HTIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, HTIE_A, O>;
181impl<'a, const O: u8> HTIE_W<'a, O> {
182    ///Half Transfer interrupt disabled
183    #[inline(always)]
184    pub fn disabled(self) -> &'a mut W {
185        self.variant(HTIE_A::Disabled)
186    }
187    ///Half Transfer interrupt enabled
188    #[inline(always)]
189    pub fn enabled(self) -> &'a mut W {
190        self.variant(HTIE_A::Enabled)
191    }
192}
193///Field `TEIE` reader - Transfer error interrupt enable
194pub type TEIE_R = crate::BitReader<TEIE_A>;
195/**Transfer error interrupt enable
196
197Value on reset: 0*/
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199pub enum TEIE_A {
200    ///0: Transfer Error interrupt disabled
201    Disabled = 0,
202    ///1: Transfer Error interrupt enabled
203    Enabled = 1,
204}
205impl From<TEIE_A> for bool {
206    #[inline(always)]
207    fn from(variant: TEIE_A) -> Self {
208        variant as u8 != 0
209    }
210}
211impl TEIE_R {
212    ///Get enumerated values variant
213    #[inline(always)]
214    pub fn variant(&self) -> TEIE_A {
215        match self.bits {
216            false => TEIE_A::Disabled,
217            true => TEIE_A::Enabled,
218        }
219    }
220    ///Checks if the value of the field is `Disabled`
221    #[inline(always)]
222    pub fn is_disabled(&self) -> bool {
223        *self == TEIE_A::Disabled
224    }
225    ///Checks if the value of the field is `Enabled`
226    #[inline(always)]
227    pub fn is_enabled(&self) -> bool {
228        *self == TEIE_A::Enabled
229    }
230}
231///Field `TEIE` writer - Transfer error interrupt enable
232pub type TEIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, TEIE_A, O>;
233impl<'a, const O: u8> TEIE_W<'a, O> {
234    ///Transfer Error interrupt disabled
235    #[inline(always)]
236    pub fn disabled(self) -> &'a mut W {
237        self.variant(TEIE_A::Disabled)
238    }
239    ///Transfer Error interrupt enabled
240    #[inline(always)]
241    pub fn enabled(self) -> &'a mut W {
242        self.variant(TEIE_A::Enabled)
243    }
244}
245///Field `DIR` reader - Data transfer direction
246pub type DIR_R = crate::BitReader<DIR_A>;
247/**Data transfer direction
248
249Value on reset: 0*/
250#[derive(Clone, Copy, Debug, PartialEq, Eq)]
251pub enum DIR_A {
252    ///0: Read from peripheral
253    FromPeripheral = 0,
254    ///1: Read from memory
255    FromMemory = 1,
256}
257impl From<DIR_A> for bool {
258    #[inline(always)]
259    fn from(variant: DIR_A) -> Self {
260        variant as u8 != 0
261    }
262}
263impl DIR_R {
264    ///Get enumerated values variant
265    #[inline(always)]
266    pub fn variant(&self) -> DIR_A {
267        match self.bits {
268            false => DIR_A::FromPeripheral,
269            true => DIR_A::FromMemory,
270        }
271    }
272    ///Checks if the value of the field is `FromPeripheral`
273    #[inline(always)]
274    pub fn is_from_peripheral(&self) -> bool {
275        *self == DIR_A::FromPeripheral
276    }
277    ///Checks if the value of the field is `FromMemory`
278    #[inline(always)]
279    pub fn is_from_memory(&self) -> bool {
280        *self == DIR_A::FromMemory
281    }
282}
283///Field `DIR` writer - Data transfer direction
284pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, DIR_A, O>;
285impl<'a, const O: u8> DIR_W<'a, O> {
286    ///Read from peripheral
287    #[inline(always)]
288    pub fn from_peripheral(self) -> &'a mut W {
289        self.variant(DIR_A::FromPeripheral)
290    }
291    ///Read from memory
292    #[inline(always)]
293    pub fn from_memory(self) -> &'a mut W {
294        self.variant(DIR_A::FromMemory)
295    }
296}
297///Field `CIRC` reader - Circular mode
298pub type CIRC_R = crate::BitReader<CIRC_A>;
299/**Circular mode
300
301Value on reset: 0*/
302#[derive(Clone, Copy, Debug, PartialEq, Eq)]
303pub enum CIRC_A {
304    ///0: Circular buffer disabled
305    Disabled = 0,
306    ///1: Circular buffer enabled
307    Enabled = 1,
308}
309impl From<CIRC_A> for bool {
310    #[inline(always)]
311    fn from(variant: CIRC_A) -> Self {
312        variant as u8 != 0
313    }
314}
315impl CIRC_R {
316    ///Get enumerated values variant
317    #[inline(always)]
318    pub fn variant(&self) -> CIRC_A {
319        match self.bits {
320            false => CIRC_A::Disabled,
321            true => CIRC_A::Enabled,
322        }
323    }
324    ///Checks if the value of the field is `Disabled`
325    #[inline(always)]
326    pub fn is_disabled(&self) -> bool {
327        *self == CIRC_A::Disabled
328    }
329    ///Checks if the value of the field is `Enabled`
330    #[inline(always)]
331    pub fn is_enabled(&self) -> bool {
332        *self == CIRC_A::Enabled
333    }
334}
335///Field `CIRC` writer - Circular mode
336pub type CIRC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, CIRC_A, O>;
337impl<'a, const O: u8> CIRC_W<'a, O> {
338    ///Circular buffer disabled
339    #[inline(always)]
340    pub fn disabled(self) -> &'a mut W {
341        self.variant(CIRC_A::Disabled)
342    }
343    ///Circular buffer enabled
344    #[inline(always)]
345    pub fn enabled(self) -> &'a mut W {
346        self.variant(CIRC_A::Enabled)
347    }
348}
349///Field `PINC` reader - Peripheral increment mode
350pub type PINC_R = crate::BitReader<PINC_A>;
351/**Peripheral increment mode
352
353Value on reset: 0*/
354#[derive(Clone, Copy, Debug, PartialEq, Eq)]
355pub enum PINC_A {
356    ///0: Increment mode disabled
357    Disabled = 0,
358    ///1: Increment mode enabled
359    Enabled = 1,
360}
361impl From<PINC_A> for bool {
362    #[inline(always)]
363    fn from(variant: PINC_A) -> Self {
364        variant as u8 != 0
365    }
366}
367impl PINC_R {
368    ///Get enumerated values variant
369    #[inline(always)]
370    pub fn variant(&self) -> PINC_A {
371        match self.bits {
372            false => PINC_A::Disabled,
373            true => PINC_A::Enabled,
374        }
375    }
376    ///Checks if the value of the field is `Disabled`
377    #[inline(always)]
378    pub fn is_disabled(&self) -> bool {
379        *self == PINC_A::Disabled
380    }
381    ///Checks if the value of the field is `Enabled`
382    #[inline(always)]
383    pub fn is_enabled(&self) -> bool {
384        *self == PINC_A::Enabled
385    }
386}
387///Field `PINC` writer - Peripheral increment mode
388pub type PINC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, PINC_A, O>;
389impl<'a, const O: u8> PINC_W<'a, O> {
390    ///Increment mode disabled
391    #[inline(always)]
392    pub fn disabled(self) -> &'a mut W {
393        self.variant(PINC_A::Disabled)
394    }
395    ///Increment mode enabled
396    #[inline(always)]
397    pub fn enabled(self) -> &'a mut W {
398        self.variant(PINC_A::Enabled)
399    }
400}
401///Field `MINC` reader - Memory increment mode
402pub use PINC_R as MINC_R;
403///Field `MINC` writer - Memory increment mode
404pub use PINC_W as MINC_W;
405///Field `PSIZE` reader - Peripheral size
406pub type PSIZE_R = crate::FieldReader<u8, PSIZE_A>;
407/**Peripheral size
408
409Value on reset: 0*/
410#[derive(Clone, Copy, Debug, PartialEq, Eq)]
411#[repr(u8)]
412pub enum PSIZE_A {
413    ///0: 8-bit size
414    Bits8 = 0,
415    ///1: 16-bit size
416    Bits16 = 1,
417    ///2: 32-bit size
418    Bits32 = 2,
419}
420impl From<PSIZE_A> for u8 {
421    #[inline(always)]
422    fn from(variant: PSIZE_A) -> Self {
423        variant as _
424    }
425}
426impl PSIZE_R {
427    ///Get enumerated values variant
428    #[inline(always)]
429    pub fn variant(&self) -> Option<PSIZE_A> {
430        match self.bits {
431            0 => Some(PSIZE_A::Bits8),
432            1 => Some(PSIZE_A::Bits16),
433            2 => Some(PSIZE_A::Bits32),
434            _ => None,
435        }
436    }
437    ///Checks if the value of the field is `Bits8`
438    #[inline(always)]
439    pub fn is_bits8(&self) -> bool {
440        *self == PSIZE_A::Bits8
441    }
442    ///Checks if the value of the field is `Bits16`
443    #[inline(always)]
444    pub fn is_bits16(&self) -> bool {
445        *self == PSIZE_A::Bits16
446    }
447    ///Checks if the value of the field is `Bits32`
448    #[inline(always)]
449    pub fn is_bits32(&self) -> bool {
450        *self == PSIZE_A::Bits32
451    }
452}
453///Field `PSIZE` writer - Peripheral size
454pub type PSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR_SPEC, u8, PSIZE_A, 2, O>;
455impl<'a, const O: u8> PSIZE_W<'a, O> {
456    ///8-bit size
457    #[inline(always)]
458    pub fn bits8(self) -> &'a mut W {
459        self.variant(PSIZE_A::Bits8)
460    }
461    ///16-bit size
462    #[inline(always)]
463    pub fn bits16(self) -> &'a mut W {
464        self.variant(PSIZE_A::Bits16)
465    }
466    ///32-bit size
467    #[inline(always)]
468    pub fn bits32(self) -> &'a mut W {
469        self.variant(PSIZE_A::Bits32)
470    }
471}
472///Field `MSIZE` reader - Memory size
473pub use PSIZE_R as MSIZE_R;
474///Field `MSIZE` writer - Memory size
475pub use PSIZE_W as MSIZE_W;
476///Field `PL` reader - Channel Priority level
477pub type PL_R = crate::FieldReader<u8, PL_A>;
478/**Channel Priority level
479
480Value on reset: 0*/
481#[derive(Clone, Copy, Debug, PartialEq, Eq)]
482#[repr(u8)]
483pub enum PL_A {
484    ///0: Low priority
485    Low = 0,
486    ///1: Medium priority
487    Medium = 1,
488    ///2: High priority
489    High = 2,
490    ///3: Very high priority
491    VeryHigh = 3,
492}
493impl From<PL_A> for u8 {
494    #[inline(always)]
495    fn from(variant: PL_A) -> Self {
496        variant as _
497    }
498}
499impl PL_R {
500    ///Get enumerated values variant
501    #[inline(always)]
502    pub fn variant(&self) -> PL_A {
503        match self.bits {
504            0 => PL_A::Low,
505            1 => PL_A::Medium,
506            2 => PL_A::High,
507            3 => PL_A::VeryHigh,
508            _ => unreachable!(),
509        }
510    }
511    ///Checks if the value of the field is `Low`
512    #[inline(always)]
513    pub fn is_low(&self) -> bool {
514        *self == PL_A::Low
515    }
516    ///Checks if the value of the field is `Medium`
517    #[inline(always)]
518    pub fn is_medium(&self) -> bool {
519        *self == PL_A::Medium
520    }
521    ///Checks if the value of the field is `High`
522    #[inline(always)]
523    pub fn is_high(&self) -> bool {
524        *self == PL_A::High
525    }
526    ///Checks if the value of the field is `VeryHigh`
527    #[inline(always)]
528    pub fn is_very_high(&self) -> bool {
529        *self == PL_A::VeryHigh
530    }
531}
532///Field `PL` writer - Channel Priority level
533pub type PL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR_SPEC, u8, PL_A, 2, O>;
534impl<'a, const O: u8> PL_W<'a, O> {
535    ///Low priority
536    #[inline(always)]
537    pub fn low(self) -> &'a mut W {
538        self.variant(PL_A::Low)
539    }
540    ///Medium priority
541    #[inline(always)]
542    pub fn medium(self) -> &'a mut W {
543        self.variant(PL_A::Medium)
544    }
545    ///High priority
546    #[inline(always)]
547    pub fn high(self) -> &'a mut W {
548        self.variant(PL_A::High)
549    }
550    ///Very high priority
551    #[inline(always)]
552    pub fn very_high(self) -> &'a mut W {
553        self.variant(PL_A::VeryHigh)
554    }
555}
556///Field `MEM2MEM` reader - Memory to memory mode
557pub type MEM2MEM_R = crate::BitReader<MEM2MEM_A>;
558/**Memory to memory mode
559
560Value on reset: 0*/
561#[derive(Clone, Copy, Debug, PartialEq, Eq)]
562pub enum MEM2MEM_A {
563    ///0: Memory to memory mode disabled
564    Disabled = 0,
565    ///1: Memory to memory mode enabled
566    Enabled = 1,
567}
568impl From<MEM2MEM_A> for bool {
569    #[inline(always)]
570    fn from(variant: MEM2MEM_A) -> Self {
571        variant as u8 != 0
572    }
573}
574impl MEM2MEM_R {
575    ///Get enumerated values variant
576    #[inline(always)]
577    pub fn variant(&self) -> MEM2MEM_A {
578        match self.bits {
579            false => MEM2MEM_A::Disabled,
580            true => MEM2MEM_A::Enabled,
581        }
582    }
583    ///Checks if the value of the field is `Disabled`
584    #[inline(always)]
585    pub fn is_disabled(&self) -> bool {
586        *self == MEM2MEM_A::Disabled
587    }
588    ///Checks if the value of the field is `Enabled`
589    #[inline(always)]
590    pub fn is_enabled(&self) -> bool {
591        *self == MEM2MEM_A::Enabled
592    }
593}
594///Field `MEM2MEM` writer - Memory to memory mode
595pub type MEM2MEM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR_SPEC, MEM2MEM_A, O>;
596impl<'a, const O: u8> MEM2MEM_W<'a, O> {
597    ///Memory to memory mode disabled
598    #[inline(always)]
599    pub fn disabled(self) -> &'a mut W {
600        self.variant(MEM2MEM_A::Disabled)
601    }
602    ///Memory to memory mode enabled
603    #[inline(always)]
604    pub fn enabled(self) -> &'a mut W {
605        self.variant(MEM2MEM_A::Enabled)
606    }
607}
608impl R {
609    ///Bit 0 - Channel enable
610    #[inline(always)]
611    pub fn en(&self) -> EN_R {
612        EN_R::new((self.bits & 1) != 0)
613    }
614    ///Bit 1 - Transfer complete interrupt enable
615    #[inline(always)]
616    pub fn tcie(&self) -> TCIE_R {
617        TCIE_R::new(((self.bits >> 1) & 1) != 0)
618    }
619    ///Bit 2 - Half Transfer interrupt enable
620    #[inline(always)]
621    pub fn htie(&self) -> HTIE_R {
622        HTIE_R::new(((self.bits >> 2) & 1) != 0)
623    }
624    ///Bit 3 - Transfer error interrupt enable
625    #[inline(always)]
626    pub fn teie(&self) -> TEIE_R {
627        TEIE_R::new(((self.bits >> 3) & 1) != 0)
628    }
629    ///Bit 4 - Data transfer direction
630    #[inline(always)]
631    pub fn dir(&self) -> DIR_R {
632        DIR_R::new(((self.bits >> 4) & 1) != 0)
633    }
634    ///Bit 5 - Circular mode
635    #[inline(always)]
636    pub fn circ(&self) -> CIRC_R {
637        CIRC_R::new(((self.bits >> 5) & 1) != 0)
638    }
639    ///Bit 6 - Peripheral increment mode
640    #[inline(always)]
641    pub fn pinc(&self) -> PINC_R {
642        PINC_R::new(((self.bits >> 6) & 1) != 0)
643    }
644    ///Bit 7 - Memory increment mode
645    #[inline(always)]
646    pub fn minc(&self) -> MINC_R {
647        MINC_R::new(((self.bits >> 7) & 1) != 0)
648    }
649    ///Bits 8:9 - Peripheral size
650    #[inline(always)]
651    pub fn psize(&self) -> PSIZE_R {
652        PSIZE_R::new(((self.bits >> 8) & 3) as u8)
653    }
654    ///Bits 10:11 - Memory size
655    #[inline(always)]
656    pub fn msize(&self) -> MSIZE_R {
657        MSIZE_R::new(((self.bits >> 10) & 3) as u8)
658    }
659    ///Bits 12:13 - Channel Priority level
660    #[inline(always)]
661    pub fn pl(&self) -> PL_R {
662        PL_R::new(((self.bits >> 12) & 3) as u8)
663    }
664    ///Bit 14 - Memory to memory mode
665    #[inline(always)]
666    pub fn mem2mem(&self) -> MEM2MEM_R {
667        MEM2MEM_R::new(((self.bits >> 14) & 1) != 0)
668    }
669}
670impl W {
671    ///Bit 0 - Channel enable
672    #[inline(always)]
673    #[must_use]
674    pub fn en(&mut self) -> EN_W<0> {
675        EN_W::new(self)
676    }
677    ///Bit 1 - Transfer complete interrupt enable
678    #[inline(always)]
679    #[must_use]
680    pub fn tcie(&mut self) -> TCIE_W<1> {
681        TCIE_W::new(self)
682    }
683    ///Bit 2 - Half Transfer interrupt enable
684    #[inline(always)]
685    #[must_use]
686    pub fn htie(&mut self) -> HTIE_W<2> {
687        HTIE_W::new(self)
688    }
689    ///Bit 3 - Transfer error interrupt enable
690    #[inline(always)]
691    #[must_use]
692    pub fn teie(&mut self) -> TEIE_W<3> {
693        TEIE_W::new(self)
694    }
695    ///Bit 4 - Data transfer direction
696    #[inline(always)]
697    #[must_use]
698    pub fn dir(&mut self) -> DIR_W<4> {
699        DIR_W::new(self)
700    }
701    ///Bit 5 - Circular mode
702    #[inline(always)]
703    #[must_use]
704    pub fn circ(&mut self) -> CIRC_W<5> {
705        CIRC_W::new(self)
706    }
707    ///Bit 6 - Peripheral increment mode
708    #[inline(always)]
709    #[must_use]
710    pub fn pinc(&mut self) -> PINC_W<6> {
711        PINC_W::new(self)
712    }
713    ///Bit 7 - Memory increment mode
714    #[inline(always)]
715    #[must_use]
716    pub fn minc(&mut self) -> MINC_W<7> {
717        MINC_W::new(self)
718    }
719    ///Bits 8:9 - Peripheral size
720    #[inline(always)]
721    #[must_use]
722    pub fn psize(&mut self) -> PSIZE_W<8> {
723        PSIZE_W::new(self)
724    }
725    ///Bits 10:11 - Memory size
726    #[inline(always)]
727    #[must_use]
728    pub fn msize(&mut self) -> MSIZE_W<10> {
729        MSIZE_W::new(self)
730    }
731    ///Bits 12:13 - Channel Priority level
732    #[inline(always)]
733    #[must_use]
734    pub fn pl(&mut self) -> PL_W<12> {
735        PL_W::new(self)
736    }
737    ///Bit 14 - Memory to memory mode
738    #[inline(always)]
739    #[must_use]
740    pub fn mem2mem(&mut self) -> MEM2MEM_W<14> {
741        MEM2MEM_W::new(self)
742    }
743    ///Writes raw bits to the register.
744    #[inline(always)]
745    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
746        self.0.bits(bits);
747        self
748    }
749}
750/**DMA channel configuration register (DMA_CCR)
751
752This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
753
754For information about available fields see [cr](index.html) module*/
755pub struct CR_SPEC;
756impl crate::RegisterSpec for CR_SPEC {
757    type Ux = u32;
758}
759///`read()` method returns [cr::R](R) reader structure
760impl crate::Readable for CR_SPEC {
761    type Reader = R;
762}
763///`write(|w| ..)` method takes [cr::W](W) writer structure
764impl crate::Writable for CR_SPEC {
765    type Writer = W;
766    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
767    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
768}
769///`reset()` method sets CR to value 0
770impl crate::Resettable for CR_SPEC {
771    const RESET_VALUE: Self::Ux = 0;
772}
py32f0/py32f003/dma/ch/cr.rs

py32f0/py32f003/dma/ch/
cr.rs
