py32f0/py32f003/dbg/
apb_fz1.rs

1///Register `APB_FZ1` reader
2pub struct R(crate::R<APB_FZ1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<APB_FZ1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<APB_FZ1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<APB_FZ1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `APB_FZ1` writer
17pub struct W(crate::W<APB_FZ1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<APB_FZ1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<APB_FZ1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<APB_FZ1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `DBG_TIMER3_STOP` reader - Debug Timer 3 stopped when Core is halted
38pub type DBG_TIMER3_STOP_R = crate::BitReader<DBG_TIMER3_STOP_A>;
39/**Debug Timer 3 stopped when Core is halted
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum DBG_TIMER3_STOP_A {
44    ///0: The counter clock of TIMx is fed even if the core is halted
45    Continue = 0,
46    ///1: The counter clock of TIMx is stopped when the core is halted
47    Stop = 1,
48}
49impl From<DBG_TIMER3_STOP_A> for bool {
50    #[inline(always)]
51    fn from(variant: DBG_TIMER3_STOP_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl DBG_TIMER3_STOP_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> DBG_TIMER3_STOP_A {
59        match self.bits {
60            false => DBG_TIMER3_STOP_A::Continue,
61            true => DBG_TIMER3_STOP_A::Stop,
62        }
63    }
64    ///Checks if the value of the field is `Continue`
65    #[inline(always)]
66    pub fn is_continue(&self) -> bool {
67        *self == DBG_TIMER3_STOP_A::Continue
68    }
69    ///Checks if the value of the field is `Stop`
70    #[inline(always)]
71    pub fn is_stop(&self) -> bool {
72        *self == DBG_TIMER3_STOP_A::Stop
73    }
74}
75///Field `DBG_TIMER3_STOP` writer - Debug Timer 3 stopped when Core is halted
76pub type DBG_TIMER3_STOP_W<'a, const O: u8> =
77    crate::BitWriter<'a, u32, APB_FZ1_SPEC, DBG_TIMER3_STOP_A, O>;
78impl<'a, const O: u8> DBG_TIMER3_STOP_W<'a, O> {
79    ///The counter clock of TIMx is fed even if the core is halted
80    #[inline(always)]
81    pub fn continue_(self) -> &'a mut W {
82        self.variant(DBG_TIMER3_STOP_A::Continue)
83    }
84    ///The counter clock of TIMx is stopped when the core is halted
85    #[inline(always)]
86    pub fn stop(self) -> &'a mut W {
87        self.variant(DBG_TIMER3_STOP_A::Stop)
88    }
89}
90///Field `DBG_RTC_STOP` reader - Debug RTC stopped when Core is halted
91pub type DBG_RTC_STOP_R = crate::BitReader<DBG_RTC_STOP_A>;
92/**Debug RTC stopped when Core is halted
93
94Value on reset: 0*/
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum DBG_RTC_STOP_A {
97    ///0: The clock of the RTC counter is fed even if the core is halted
98    Continue = 0,
99    ///1: The clock of the RTC counter is stopped when the core is halted
100    Stop = 1,
101}
102impl From<DBG_RTC_STOP_A> for bool {
103    #[inline(always)]
104    fn from(variant: DBG_RTC_STOP_A) -> Self {
105        variant as u8 != 0
106    }
107}
108impl DBG_RTC_STOP_R {
109    ///Get enumerated values variant
110    #[inline(always)]
111    pub fn variant(&self) -> DBG_RTC_STOP_A {
112        match self.bits {
113            false => DBG_RTC_STOP_A::Continue,
114            true => DBG_RTC_STOP_A::Stop,
115        }
116    }
117    ///Checks if the value of the field is `Continue`
118    #[inline(always)]
119    pub fn is_continue(&self) -> bool {
120        *self == DBG_RTC_STOP_A::Continue
121    }
122    ///Checks if the value of the field is `Stop`
123    #[inline(always)]
124    pub fn is_stop(&self) -> bool {
125        *self == DBG_RTC_STOP_A::Stop
126    }
127}
128///Field `DBG_RTC_STOP` writer - Debug RTC stopped when Core is halted
129pub type DBG_RTC_STOP_W<'a, const O: u8> =
130    crate::BitWriter<'a, u32, APB_FZ1_SPEC, DBG_RTC_STOP_A, O>;
131impl<'a, const O: u8> DBG_RTC_STOP_W<'a, O> {
132    ///The clock of the RTC counter is fed even if the core is halted
133    #[inline(always)]
134    pub fn continue_(self) -> &'a mut W {
135        self.variant(DBG_RTC_STOP_A::Continue)
136    }
137    ///The clock of the RTC counter is stopped when the core is halted
138    #[inline(always)]
139    pub fn stop(self) -> &'a mut W {
140        self.variant(DBG_RTC_STOP_A::Stop)
141    }
142}
143///Field `DBG_WWDG_STOP` reader - Debug Window Wachdog stopped when Core is halted
144pub type DBG_WWDG_STOP_R = crate::BitReader<DBG_WWDG_STOP_A>;
145/**Debug Window Wachdog stopped when Core is halted
146
147Value on reset: 0*/
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149pub enum DBG_WWDG_STOP_A {
150    ///0: The window watchdog counter clock continues even if the core is halted
151    Continue = 0,
152    ///1: The window watchdog counter clock is stopped when the core is halted
153    Stop = 1,
154}
155impl From<DBG_WWDG_STOP_A> for bool {
156    #[inline(always)]
157    fn from(variant: DBG_WWDG_STOP_A) -> Self {
158        variant as u8 != 0
159    }
160}
161impl DBG_WWDG_STOP_R {
162    ///Get enumerated values variant
163    #[inline(always)]
164    pub fn variant(&self) -> DBG_WWDG_STOP_A {
165        match self.bits {
166            false => DBG_WWDG_STOP_A::Continue,
167            true => DBG_WWDG_STOP_A::Stop,
168        }
169    }
170    ///Checks if the value of the field is `Continue`
171    #[inline(always)]
172    pub fn is_continue(&self) -> bool {
173        *self == DBG_WWDG_STOP_A::Continue
174    }
175    ///Checks if the value of the field is `Stop`
176    #[inline(always)]
177    pub fn is_stop(&self) -> bool {
178        *self == DBG_WWDG_STOP_A::Stop
179    }
180}
181///Field `DBG_WWDG_STOP` writer - Debug Window Wachdog stopped when Core is halted
182pub type DBG_WWDG_STOP_W<'a, const O: u8> =
183    crate::BitWriter<'a, u32, APB_FZ1_SPEC, DBG_WWDG_STOP_A, O>;
184impl<'a, const O: u8> DBG_WWDG_STOP_W<'a, O> {
185    ///The window watchdog counter clock continues even if the core is halted
186    #[inline(always)]
187    pub fn continue_(self) -> &'a mut W {
188        self.variant(DBG_WWDG_STOP_A::Continue)
189    }
190    ///The window watchdog counter clock is stopped when the core is halted
191    #[inline(always)]
192    pub fn stop(self) -> &'a mut W {
193        self.variant(DBG_WWDG_STOP_A::Stop)
194    }
195}
196///Field `DBG_IWDG_STOP` reader - Debug Independent Wachdog stopped when Core is halted
197pub type DBG_IWDG_STOP_R = crate::BitReader<DBG_IWDG_STOP_A>;
198/**Debug Independent Wachdog stopped when Core is halted
199
200Value on reset: 0*/
201#[derive(Clone, Copy, Debug, PartialEq, Eq)]
202pub enum DBG_IWDG_STOP_A {
203    ///0: The independent watchdog counter clock continues even if the core is halted
204    Continue = 0,
205    ///1: The independent watchdog counter clock is stopped when the core is halted
206    Stop = 1,
207}
208impl From<DBG_IWDG_STOP_A> for bool {
209    #[inline(always)]
210    fn from(variant: DBG_IWDG_STOP_A) -> Self {
211        variant as u8 != 0
212    }
213}
214impl DBG_IWDG_STOP_R {
215    ///Get enumerated values variant
216    #[inline(always)]
217    pub fn variant(&self) -> DBG_IWDG_STOP_A {
218        match self.bits {
219            false => DBG_IWDG_STOP_A::Continue,
220            true => DBG_IWDG_STOP_A::Stop,
221        }
222    }
223    ///Checks if the value of the field is `Continue`
224    #[inline(always)]
225    pub fn is_continue(&self) -> bool {
226        *self == DBG_IWDG_STOP_A::Continue
227    }
228    ///Checks if the value of the field is `Stop`
229    #[inline(always)]
230    pub fn is_stop(&self) -> bool {
231        *self == DBG_IWDG_STOP_A::Stop
232    }
233}
234///Field `DBG_IWDG_STOP` writer - Debug Independent Wachdog stopped when Core is halted
235pub type DBG_IWDG_STOP_W<'a, const O: u8> =
236    crate::BitWriter<'a, u32, APB_FZ1_SPEC, DBG_IWDG_STOP_A, O>;
237impl<'a, const O: u8> DBG_IWDG_STOP_W<'a, O> {
238    ///The independent watchdog counter clock continues even if the core is halted
239    #[inline(always)]
240    pub fn continue_(self) -> &'a mut W {
241        self.variant(DBG_IWDG_STOP_A::Continue)
242    }
243    ///The independent watchdog counter clock is stopped when the core is halted
244    #[inline(always)]
245    pub fn stop(self) -> &'a mut W {
246        self.variant(DBG_IWDG_STOP_A::Stop)
247    }
248}
249///Field `DBG_LPTIM_STOP` reader - Debug LPTIM stopped when Core is halted
250pub type DBG_LPTIM_STOP_R = crate::BitReader<DBG_LPTIM_STOP_A>;
251/**Debug LPTIM stopped when Core is halted
252
253Value on reset: 0*/
254#[derive(Clone, Copy, Debug, PartialEq, Eq)]
255pub enum DBG_LPTIM_STOP_A {
256    ///0: LPTIMx counter clock is fed even if the core is halted
257    Continue = 0,
258    ///1: LPTIMx counter clock is stopped when the core is halted
259    Stop = 1,
260}
261impl From<DBG_LPTIM_STOP_A> for bool {
262    #[inline(always)]
263    fn from(variant: DBG_LPTIM_STOP_A) -> Self {
264        variant as u8 != 0
265    }
266}
267impl DBG_LPTIM_STOP_R {
268    ///Get enumerated values variant
269    #[inline(always)]
270    pub fn variant(&self) -> DBG_LPTIM_STOP_A {
271        match self.bits {
272            false => DBG_LPTIM_STOP_A::Continue,
273            true => DBG_LPTIM_STOP_A::Stop,
274        }
275    }
276    ///Checks if the value of the field is `Continue`
277    #[inline(always)]
278    pub fn is_continue(&self) -> bool {
279        *self == DBG_LPTIM_STOP_A::Continue
280    }
281    ///Checks if the value of the field is `Stop`
282    #[inline(always)]
283    pub fn is_stop(&self) -> bool {
284        *self == DBG_LPTIM_STOP_A::Stop
285    }
286}
287///Field `DBG_LPTIM_STOP` writer - Debug LPTIM stopped when Core is halted
288pub type DBG_LPTIM_STOP_W<'a, const O: u8> =
289    crate::BitWriter<'a, u32, APB_FZ1_SPEC, DBG_LPTIM_STOP_A, O>;
290impl<'a, const O: u8> DBG_LPTIM_STOP_W<'a, O> {
291    ///LPTIMx counter clock is fed even if the core is halted
292    #[inline(always)]
293    pub fn continue_(self) -> &'a mut W {
294        self.variant(DBG_LPTIM_STOP_A::Continue)
295    }
296    ///LPTIMx counter clock is stopped when the core is halted
297    #[inline(always)]
298    pub fn stop(self) -> &'a mut W {
299        self.variant(DBG_LPTIM_STOP_A::Stop)
300    }
301}
302impl R {
303    ///Bit 1 - Debug Timer 3 stopped when Core is halted
304    #[inline(always)]
305    pub fn dbg_timer3_stop(&self) -> DBG_TIMER3_STOP_R {
306        DBG_TIMER3_STOP_R::new(((self.bits >> 1) & 1) != 0)
307    }
308    ///Bit 10 - Debug RTC stopped when Core is halted
309    #[inline(always)]
310    pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R {
311        DBG_RTC_STOP_R::new(((self.bits >> 10) & 1) != 0)
312    }
313    ///Bit 11 - Debug Window Wachdog stopped when Core is halted
314    #[inline(always)]
315    pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R {
316        DBG_WWDG_STOP_R::new(((self.bits >> 11) & 1) != 0)
317    }
318    ///Bit 12 - Debug Independent Wachdog stopped when Core is halted
319    #[inline(always)]
320    pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R {
321        DBG_IWDG_STOP_R::new(((self.bits >> 12) & 1) != 0)
322    }
323    ///Bit 31 - Debug LPTIM stopped when Core is halted
324    #[inline(always)]
325    pub fn dbg_lptim_stop(&self) -> DBG_LPTIM_STOP_R {
326        DBG_LPTIM_STOP_R::new(((self.bits >> 31) & 1) != 0)
327    }
328}
329impl W {
330    ///Bit 1 - Debug Timer 3 stopped when Core is halted
331    #[inline(always)]
332    #[must_use]
333    pub fn dbg_timer3_stop(&mut self) -> DBG_TIMER3_STOP_W<1> {
334        DBG_TIMER3_STOP_W::new(self)
335    }
336    ///Bit 10 - Debug RTC stopped when Core is halted
337    #[inline(always)]
338    #[must_use]
339    pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W<10> {
340        DBG_RTC_STOP_W::new(self)
341    }
342    ///Bit 11 - Debug Window Wachdog stopped when Core is halted
343    #[inline(always)]
344    #[must_use]
345    pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W<11> {
346        DBG_WWDG_STOP_W::new(self)
347    }
348    ///Bit 12 - Debug Independent Wachdog stopped when Core is halted
349    #[inline(always)]
350    #[must_use]
351    pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W<12> {
352        DBG_IWDG_STOP_W::new(self)
353    }
354    ///Bit 31 - Debug LPTIM stopped when Core is halted
355    #[inline(always)]
356    #[must_use]
357    pub fn dbg_lptim_stop(&mut self) -> DBG_LPTIM_STOP_W<31> {
358        DBG_LPTIM_STOP_W::new(self)
359    }
360    ///Writes raw bits to the register.
361    #[inline(always)]
362    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
363        self.0.bits(bits);
364        self
365    }
366}
367/**APB Freeze Register1
368
369This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
370
371For information about available fields see [apb_fz1](index.html) module*/
372pub struct APB_FZ1_SPEC;
373impl crate::RegisterSpec for APB_FZ1_SPEC {
374    type Ux = u32;
375}
376///`read()` method returns [apb_fz1::R](R) reader structure
377impl crate::Readable for APB_FZ1_SPEC {
378    type Reader = R;
379}
380///`write(|w| ..)` method takes [apb_fz1::W](W) writer structure
381impl crate::Writable for APB_FZ1_SPEC {
382    type Writer = W;
383    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
384    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
385}
386///`reset()` method sets APB_FZ1 to value 0
387impl crate::Resettable for APB_FZ1_SPEC {
388    const RESET_VALUE: Self::Ux = 0;
389}
py32f0/py32f003/dbg/apb_fz1.rs

py32f0/py32f003/dbg/
apb_fz1.rs
