py32f0/py32f002b/tim14/
sr.rs

1///Register `SR` reader
2pub struct R(crate::R<SR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `SR` writer
17pub struct W(crate::W<SR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `UIF` reader - desc UIF
38pub type UIF_R = crate::BitReader<bool>;
39///Field `UIF` writer - desc UIF
40pub type UIF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
41///Field `CC1IF` reader - desc CC1IF
42pub type CC1IF_R = crate::BitReader<bool>;
43///Field `CC1IF` writer - desc CC1IF
44pub type CC1IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
45///Field `CC1OF` reader - desc CC1OF
46pub type CC1OF_R = crate::BitReader<bool>;
47///Field `CC1OF` writer - desc CC1OF
48pub type CC1OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
49///Field `IC1IR` reader - desc IC1IR
50pub type IC1IR_R = crate::BitReader<bool>;
51///Field `IC1IR` writer - desc IC1IR
52pub type IC1IR_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
53///Field `IC1IF` reader - desc IC1IF
54pub type IC1IF_R = crate::BitReader<bool>;
55///Field `IC1IF` writer - desc IC1IF
56pub type IC1IF_W<'a, const O: u8> = crate::BitWriter<'a, u32, SR_SPEC, bool, O>;
57impl R {
58    ///Bit 0 - desc UIF
59    #[inline(always)]
60    pub fn uif(&self) -> UIF_R {
61        UIF_R::new((self.bits & 1) != 0)
62    }
63    ///Bit 1 - desc CC1IF
64    #[inline(always)]
65    pub fn cc1if(&self) -> CC1IF_R {
66        CC1IF_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    ///Bit 9 - desc CC1OF
69    #[inline(always)]
70    pub fn cc1of(&self) -> CC1OF_R {
71        CC1OF_R::new(((self.bits >> 9) & 1) != 0)
72    }
73    ///Bit 16 - desc IC1IR
74    #[inline(always)]
75    pub fn ic1ir(&self) -> IC1IR_R {
76        IC1IR_R::new(((self.bits >> 16) & 1) != 0)
77    }
78    ///Bit 20 - desc IC1IF
79    #[inline(always)]
80    pub fn ic1if(&self) -> IC1IF_R {
81        IC1IF_R::new(((self.bits >> 20) & 1) != 0)
82    }
83}
84impl W {
85    ///Bit 0 - desc UIF
86    #[inline(always)]
87    #[must_use]
88    pub fn uif(&mut self) -> UIF_W<0> {
89        UIF_W::new(self)
90    }
91    ///Bit 1 - desc CC1IF
92    #[inline(always)]
93    #[must_use]
94    pub fn cc1if(&mut self) -> CC1IF_W<1> {
95        CC1IF_W::new(self)
96    }
97    ///Bit 9 - desc CC1OF
98    #[inline(always)]
99    #[must_use]
100    pub fn cc1of(&mut self) -> CC1OF_W<9> {
101        CC1OF_W::new(self)
102    }
103    ///Bit 16 - desc IC1IR
104    #[inline(always)]
105    #[must_use]
106    pub fn ic1ir(&mut self) -> IC1IR_W<16> {
107        IC1IR_W::new(self)
108    }
109    ///Bit 20 - desc IC1IF
110    #[inline(always)]
111    #[must_use]
112    pub fn ic1if(&mut self) -> IC1IF_W<20> {
113        IC1IF_W::new(self)
114    }
115    ///Writes raw bits to the register.
116    #[inline(always)]
117    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
118        self.0.bits(bits);
119        self
120    }
121}
122/**desc SR
123
124This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
125
126For information about available fields see [sr](index.html) module*/
127pub struct SR_SPEC;
128impl crate::RegisterSpec for SR_SPEC {
129    type Ux = u32;
130}
131///`read()` method returns [sr::R](R) reader structure
132impl crate::Readable for SR_SPEC {
133    type Reader = R;
134}
135///`write(|w| ..)` method takes [sr::W](W) writer structure
136impl crate::Writable for SR_SPEC {
137    type Writer = W;
138    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
139    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
140}
141///`reset()` method sets SR to value 0
142impl crate::Resettable for SR_SPEC {
143    const RESET_VALUE: Self::Ux = 0;
144}
py32f0/py32f002b/tim14/sr.rs

py32f0/py32f002b/tim14/
sr.rs
