py32f0/py32f002b/tim1/
cr2.rs

1///Register `CR2` reader
2pub struct R(crate::R<CR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR2` writer
17pub struct W(crate::W<CR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CCPC` reader - desc CCPC
38pub type CCPC_R = crate::BitReader<bool>;
39///Field `CCPC` writer - desc CCPC
40pub type CCPC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
41///Field `CCUS` reader - desc CCUS
42pub type CCUS_R = crate::BitReader<CCUS_A>;
43/**desc CCUS
44
45Value on reset: 0*/
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum CCUS_A {
48    ///0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
49    Bit = 0,
50    ///1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
51    BitOrEdge = 1,
52}
53impl From<CCUS_A> for bool {
54    #[inline(always)]
55    fn from(variant: CCUS_A) -> Self {
56        variant as u8 != 0
57    }
58}
59impl CCUS_R {
60    ///Get enumerated values variant
61    #[inline(always)]
62    pub fn variant(&self) -> CCUS_A {
63        match self.bits {
64            false => CCUS_A::Bit,
65            true => CCUS_A::BitOrEdge,
66        }
67    }
68    ///Checks if the value of the field is `Bit`
69    #[inline(always)]
70    pub fn is_bit_(&self) -> bool {
71        *self == CCUS_A::Bit
72    }
73    ///Checks if the value of the field is `BitOrEdge`
74    #[inline(always)]
75    pub fn is_bit_or_edge(&self) -> bool {
76        *self == CCUS_A::BitOrEdge
77    }
78}
79///Field `CCUS` writer - desc CCUS
80pub type CCUS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, CCUS_A, O>;
81impl<'a, const O: u8> CCUS_W<'a, O> {
82    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
83    #[inline(always)]
84    pub fn bit_(self) -> &'a mut W {
85        self.variant(CCUS_A::Bit)
86    }
87    ///When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
88    #[inline(always)]
89    pub fn bit_or_edge(self) -> &'a mut W {
90        self.variant(CCUS_A::BitOrEdge)
91    }
92}
93///Field `MMS` reader - desc MMS
94pub type MMS_R = crate::FieldReader<u8, MMS_A>;
95/**desc MMS
96
97Value on reset: 0*/
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99#[repr(u8)]
100pub enum MMS_A {
101    ///0: The UG bit from the TIMx_EGR register is used as trigger output
102    Reset = 0,
103    ///1: The counter enable signal, CNT_EN, is used as trigger output
104    Enable = 1,
105    ///2: The update event is selected as trigger output
106    Update = 2,
107    ///3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
108    ComparePulse = 3,
109    ///4: OC1REF signal is used as trigger output
110    CompareOc1 = 4,
111    ///5: OC2REF signal is used as trigger output
112    CompareOc2 = 5,
113    ///6: OC3REF signal is used as trigger output
114    CompareOc3 = 6,
115    ///7: OC4REF signal is used as trigger output
116    CompareOc4 = 7,
117}
118impl From<MMS_A> for u8 {
119    #[inline(always)]
120    fn from(variant: MMS_A) -> Self {
121        variant as _
122    }
123}
124impl MMS_R {
125    ///Get enumerated values variant
126    #[inline(always)]
127    pub fn variant(&self) -> MMS_A {
128        match self.bits {
129            0 => MMS_A::Reset,
130            1 => MMS_A::Enable,
131            2 => MMS_A::Update,
132            3 => MMS_A::ComparePulse,
133            4 => MMS_A::CompareOc1,
134            5 => MMS_A::CompareOc2,
135            6 => MMS_A::CompareOc3,
136            7 => MMS_A::CompareOc4,
137            _ => unreachable!(),
138        }
139    }
140    ///Checks if the value of the field is `Reset`
141    #[inline(always)]
142    pub fn is_reset(&self) -> bool {
143        *self == MMS_A::Reset
144    }
145    ///Checks if the value of the field is `Enable`
146    #[inline(always)]
147    pub fn is_enable(&self) -> bool {
148        *self == MMS_A::Enable
149    }
150    ///Checks if the value of the field is `Update`
151    #[inline(always)]
152    pub fn is_update(&self) -> bool {
153        *self == MMS_A::Update
154    }
155    ///Checks if the value of the field is `ComparePulse`
156    #[inline(always)]
157    pub fn is_compare_pulse(&self) -> bool {
158        *self == MMS_A::ComparePulse
159    }
160    ///Checks if the value of the field is `CompareOc1`
161    #[inline(always)]
162    pub fn is_compare_oc1(&self) -> bool {
163        *self == MMS_A::CompareOc1
164    }
165    ///Checks if the value of the field is `CompareOc2`
166    #[inline(always)]
167    pub fn is_compare_oc2(&self) -> bool {
168        *self == MMS_A::CompareOc2
169    }
170    ///Checks if the value of the field is `CompareOc3`
171    #[inline(always)]
172    pub fn is_compare_oc3(&self) -> bool {
173        *self == MMS_A::CompareOc3
174    }
175    ///Checks if the value of the field is `CompareOc4`
176    #[inline(always)]
177    pub fn is_compare_oc4(&self) -> bool {
178        *self == MMS_A::CompareOc4
179    }
180}
181///Field `MMS` writer - desc MMS
182pub type MMS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CR2_SPEC, u8, MMS_A, 3, O>;
183impl<'a, const O: u8> MMS_W<'a, O> {
184    ///The UG bit from the TIMx_EGR register is used as trigger output
185    #[inline(always)]
186    pub fn reset(self) -> &'a mut W {
187        self.variant(MMS_A::Reset)
188    }
189    ///The counter enable signal, CNT_EN, is used as trigger output
190    #[inline(always)]
191    pub fn enable(self) -> &'a mut W {
192        self.variant(MMS_A::Enable)
193    }
194    ///The update event is selected as trigger output
195    #[inline(always)]
196    pub fn update(self) -> &'a mut W {
197        self.variant(MMS_A::Update)
198    }
199    ///The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
200    #[inline(always)]
201    pub fn compare_pulse(self) -> &'a mut W {
202        self.variant(MMS_A::ComparePulse)
203    }
204    ///OC1REF signal is used as trigger output
205    #[inline(always)]
206    pub fn compare_oc1(self) -> &'a mut W {
207        self.variant(MMS_A::CompareOc1)
208    }
209    ///OC2REF signal is used as trigger output
210    #[inline(always)]
211    pub fn compare_oc2(self) -> &'a mut W {
212        self.variant(MMS_A::CompareOc2)
213    }
214    ///OC3REF signal is used as trigger output
215    #[inline(always)]
216    pub fn compare_oc3(self) -> &'a mut W {
217        self.variant(MMS_A::CompareOc3)
218    }
219    ///OC4REF signal is used as trigger output
220    #[inline(always)]
221    pub fn compare_oc4(self) -> &'a mut W {
222        self.variant(MMS_A::CompareOc4)
223    }
224}
225///Field `TI1S` reader - desc TI1S
226pub type TI1S_R = crate::BitReader<TI1S_A>;
227/**desc TI1S
228
229Value on reset: 0*/
230#[derive(Clone, Copy, Debug, PartialEq, Eq)]
231pub enum TI1S_A {
232    ///0: The TIMx_CH1 pin is connected to TI1 input
233    Normal = 0,
234    ///1: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
235    Xor = 1,
236}
237impl From<TI1S_A> for bool {
238    #[inline(always)]
239    fn from(variant: TI1S_A) -> Self {
240        variant as u8 != 0
241    }
242}
243impl TI1S_R {
244    ///Get enumerated values variant
245    #[inline(always)]
246    pub fn variant(&self) -> TI1S_A {
247        match self.bits {
248            false => TI1S_A::Normal,
249            true => TI1S_A::Xor,
250        }
251    }
252    ///Checks if the value of the field is `Normal`
253    #[inline(always)]
254    pub fn is_normal(&self) -> bool {
255        *self == TI1S_A::Normal
256    }
257    ///Checks if the value of the field is `Xor`
258    #[inline(always)]
259    pub fn is_xor(&self) -> bool {
260        *self == TI1S_A::Xor
261    }
262}
263///Field `TI1S` writer - desc TI1S
264pub type TI1S_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, TI1S_A, O>;
265impl<'a, const O: u8> TI1S_W<'a, O> {
266    ///The TIMx_CH1 pin is connected to TI1 input
267    #[inline(always)]
268    pub fn normal(self) -> &'a mut W {
269        self.variant(TI1S_A::Normal)
270    }
271    ///The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
272    #[inline(always)]
273    pub fn xor(self) -> &'a mut W {
274        self.variant(TI1S_A::Xor)
275    }
276}
277///Field `OIS1` reader - desc OIS1
278pub type OIS1_R = crate::BitReader<bool>;
279///Field `OIS1` writer - desc OIS1
280pub type OIS1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
281///Field `OIS1N` reader - desc OIS1N
282pub type OIS1N_R = crate::BitReader<bool>;
283///Field `OIS1N` writer - desc OIS1N
284pub type OIS1N_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
285///Field `OIS2` reader - desc OIS2
286pub type OIS2_R = crate::BitReader<bool>;
287///Field `OIS2` writer - desc OIS2
288pub type OIS2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
289///Field `OIS2N` reader - desc OIS2N
290pub type OIS2N_R = crate::BitReader<bool>;
291///Field `OIS2N` writer - desc OIS2N
292pub type OIS2N_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
293///Field `OIS3` reader - desc OIS3
294pub type OIS3_R = crate::BitReader<bool>;
295///Field `OIS3` writer - desc OIS3
296pub type OIS3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
297///Field `OIS3N` reader - desc OIS3N
298pub type OIS3N_R = crate::BitReader<bool>;
299///Field `OIS3N` writer - desc OIS3N
300pub type OIS3N_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
301///Field `OIS4` reader - desc OIS4
302pub type OIS4_R = crate::BitReader<bool>;
303///Field `OIS4` writer - desc OIS4
304pub type OIS4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR2_SPEC, bool, O>;
305impl R {
306    ///Bit 0 - desc CCPC
307    #[inline(always)]
308    pub fn ccpc(&self) -> CCPC_R {
309        CCPC_R::new((self.bits & 1) != 0)
310    }
311    ///Bit 2 - desc CCUS
312    #[inline(always)]
313    pub fn ccus(&self) -> CCUS_R {
314        CCUS_R::new(((self.bits >> 2) & 1) != 0)
315    }
316    ///Bits 4:6 - desc MMS
317    #[inline(always)]
318    pub fn mms(&self) -> MMS_R {
319        MMS_R::new(((self.bits >> 4) & 7) as u8)
320    }
321    ///Bit 7 - desc TI1S
322    #[inline(always)]
323    pub fn ti1s(&self) -> TI1S_R {
324        TI1S_R::new(((self.bits >> 7) & 1) != 0)
325    }
326    ///Bit 8 - desc OIS1
327    #[inline(always)]
328    pub fn ois1(&self) -> OIS1_R {
329        OIS1_R::new(((self.bits >> 8) & 1) != 0)
330    }
331    ///Bit 9 - desc OIS1N
332    #[inline(always)]
333    pub fn ois1n(&self) -> OIS1N_R {
334        OIS1N_R::new(((self.bits >> 9) & 1) != 0)
335    }
336    ///Bit 10 - desc OIS2
337    #[inline(always)]
338    pub fn ois2(&self) -> OIS2_R {
339        OIS2_R::new(((self.bits >> 10) & 1) != 0)
340    }
341    ///Bit 11 - desc OIS2N
342    #[inline(always)]
343    pub fn ois2n(&self) -> OIS2N_R {
344        OIS2N_R::new(((self.bits >> 11) & 1) != 0)
345    }
346    ///Bit 12 - desc OIS3
347    #[inline(always)]
348    pub fn ois3(&self) -> OIS3_R {
349        OIS3_R::new(((self.bits >> 12) & 1) != 0)
350    }
351    ///Bit 13 - desc OIS3N
352    #[inline(always)]
353    pub fn ois3n(&self) -> OIS3N_R {
354        OIS3N_R::new(((self.bits >> 13) & 1) != 0)
355    }
356    ///Bit 14 - desc OIS4
357    #[inline(always)]
358    pub fn ois4(&self) -> OIS4_R {
359        OIS4_R::new(((self.bits >> 14) & 1) != 0)
360    }
361}
362impl W {
363    ///Bit 0 - desc CCPC
364    #[inline(always)]
365    #[must_use]
366    pub fn ccpc(&mut self) -> CCPC_W<0> {
367        CCPC_W::new(self)
368    }
369    ///Bit 2 - desc CCUS
370    #[inline(always)]
371    #[must_use]
372    pub fn ccus(&mut self) -> CCUS_W<2> {
373        CCUS_W::new(self)
374    }
375    ///Bits 4:6 - desc MMS
376    #[inline(always)]
377    #[must_use]
378    pub fn mms(&mut self) -> MMS_W<4> {
379        MMS_W::new(self)
380    }
381    ///Bit 7 - desc TI1S
382    #[inline(always)]
383    #[must_use]
384    pub fn ti1s(&mut self) -> TI1S_W<7> {
385        TI1S_W::new(self)
386    }
387    ///Bit 8 - desc OIS1
388    #[inline(always)]
389    #[must_use]
390    pub fn ois1(&mut self) -> OIS1_W<8> {
391        OIS1_W::new(self)
392    }
393    ///Bit 9 - desc OIS1N
394    #[inline(always)]
395    #[must_use]
396    pub fn ois1n(&mut self) -> OIS1N_W<9> {
397        OIS1N_W::new(self)
398    }
399    ///Bit 10 - desc OIS2
400    #[inline(always)]
401    #[must_use]
402    pub fn ois2(&mut self) -> OIS2_W<10> {
403        OIS2_W::new(self)
404    }
405    ///Bit 11 - desc OIS2N
406    #[inline(always)]
407    #[must_use]
408    pub fn ois2n(&mut self) -> OIS2N_W<11> {
409        OIS2N_W::new(self)
410    }
411    ///Bit 12 - desc OIS3
412    #[inline(always)]
413    #[must_use]
414    pub fn ois3(&mut self) -> OIS3_W<12> {
415        OIS3_W::new(self)
416    }
417    ///Bit 13 - desc OIS3N
418    #[inline(always)]
419    #[must_use]
420    pub fn ois3n(&mut self) -> OIS3N_W<13> {
421        OIS3N_W::new(self)
422    }
423    ///Bit 14 - desc OIS4
424    #[inline(always)]
425    #[must_use]
426    pub fn ois4(&mut self) -> OIS4_W<14> {
427        OIS4_W::new(self)
428    }
429    ///Writes raw bits to the register.
430    #[inline(always)]
431    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
432        self.0.bits(bits);
433        self
434    }
435}
436/**desc CR2
437
438This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
439
440For information about available fields see [cr2](index.html) module*/
441pub struct CR2_SPEC;
442impl crate::RegisterSpec for CR2_SPEC {
443    type Ux = u32;
444}
445///`read()` method returns [cr2::R](R) reader structure
446impl crate::Readable for CR2_SPEC {
447    type Reader = R;
448}
449///`write(|w| ..)` method takes [cr2::W](W) writer structure
450impl crate::Writable for CR2_SPEC {
451    type Writer = W;
452    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
453    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
454}
455///`reset()` method sets CR2 to value 0
456impl crate::Resettable for CR2_SPEC {
457    const RESET_VALUE: Self::Ux = 0;
458}
py32f0/py32f002b/tim1/cr2.rs

py32f0/py32f002b/tim1/
cr2.rs
