py32f0/py32f002b/
tim1.rs

1///Register block
2#[repr(C)]
3pub struct RegisterBlock {
4    ///0x00 - desc CR1
5    pub cr1: CR1,
6    ///0x04 - desc CR2
7    pub cr2: CR2,
8    ///0x08 - desc SMCR
9    pub smcr: SMCR,
10    ///0x0c - desc DIER
11    pub dier: DIER,
12    ///0x10 - desc SR
13    pub sr: SR,
14    ///0x14 - desc EGR
15    pub egr: EGR,
16    _reserved_6_ccmr1: [u8; 0x04],
17    _reserved_7_ccmr2: [u8; 0x04],
18    ///0x20 - desc CCER
19    pub ccer: CCER,
20    ///0x24 - desc CNT
21    pub cnt: CNT,
22    ///0x28 - desc PSC
23    pub psc: PSC,
24    ///0x2c - desc ARR
25    pub arr: ARR,
26    ///0x30 - desc RCR
27    pub rcr: RCR,
28    ///0x34..0x44 - desc CCR%s
29    pub ccr: [CCR; 4],
30    ///0x44 - desc BDTR
31    pub bdtr: BDTR,
32}
33impl RegisterBlock {
34    ///0x18 - desc CCMR1:INPUT
35    #[inline(always)]
36    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
37        unsafe { &*(self as *const Self).cast::<u8>().add(24usize).cast() }
38    }
39    ///0x18 - desc CCMR1:OUTPUT
40    #[inline(always)]
41    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
42        unsafe { &*(self as *const Self).cast::<u8>().add(24usize).cast() }
43    }
44    ///0x1c - desc CCMR2:INPUT
45    #[inline(always)]
46    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
47        unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
48    }
49    ///0x1c - desc CCMR2:OUTPUT
50    #[inline(always)]
51    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
52        unsafe { &*(self as *const Self).cast::<u8>().add(28usize).cast() }
53    }
54    ///0x34 - desc CCR%s
55    #[inline(always)]
56    pub fn ccr1(&self) -> &CCR {
57        &self.ccr[0]
58    }
59    ///0x38 - desc CCR%s
60    #[inline(always)]
61    pub fn ccr2(&self) -> &CCR {
62        &self.ccr[1]
63    }
64    ///0x3c - desc CCR%s
65    #[inline(always)]
66    pub fn ccr3(&self) -> &CCR {
67        &self.ccr[2]
68    }
69    ///0x40 - desc CCR%s
70    #[inline(always)]
71    pub fn ccr4(&self) -> &CCR {
72        &self.ccr[3]
73    }
74}
75///CR1 (rw) register accessor: an alias for `Reg<CR1_SPEC>`
76pub type CR1 = crate::Reg<cr1::CR1_SPEC>;
77///desc CR1
78pub mod cr1;
79///CR2 (rw) register accessor: an alias for `Reg<CR2_SPEC>`
80pub type CR2 = crate::Reg<cr2::CR2_SPEC>;
81///desc CR2
82pub mod cr2;
83///SMCR (rw) register accessor: an alias for `Reg<SMCR_SPEC>`
84pub type SMCR = crate::Reg<smcr::SMCR_SPEC>;
85///desc SMCR
86pub mod smcr;
87///DIER (rw) register accessor: an alias for `Reg<DIER_SPEC>`
88pub type DIER = crate::Reg<dier::DIER_SPEC>;
89///desc DIER
90pub mod dier;
91///SR (rw) register accessor: an alias for `Reg<SR_SPEC>`
92pub type SR = crate::Reg<sr::SR_SPEC>;
93///desc SR
94pub mod sr;
95///EGR (w) register accessor: an alias for `Reg<EGR_SPEC>`
96pub type EGR = crate::Reg<egr::EGR_SPEC>;
97///desc EGR
98pub mod egr;
99///CCMR1_OUTPUT (rw) register accessor: an alias for `Reg<CCMR1_OUTPUT_SPEC>`
100pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUT_SPEC>;
101///desc CCMR1:OUTPUT
102pub mod ccmr1_output;
103///CCMR1_INPUT (rw) register accessor: an alias for `Reg<CCMR1_INPUT_SPEC>`
104pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUT_SPEC>;
105///desc CCMR1:INPUT
106pub mod ccmr1_input;
107///CCMR2_OUTPUT (rw) register accessor: an alias for `Reg<CCMR2_OUTPUT_SPEC>`
108pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUT_SPEC>;
109///desc CCMR2:OUTPUT
110pub mod ccmr2_output;
111///CCMR2_INPUT (rw) register accessor: an alias for `Reg<CCMR2_INPUT_SPEC>`
112pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUT_SPEC>;
113///desc CCMR2:INPUT
114pub mod ccmr2_input;
115///CCER (rw) register accessor: an alias for `Reg<CCER_SPEC>`
116pub type CCER = crate::Reg<ccer::CCER_SPEC>;
117///desc CCER
118pub mod ccer;
119///CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`
120pub type CNT = crate::Reg<cnt::CNT_SPEC>;
121///desc CNT
122pub mod cnt;
123///PSC (rw) register accessor: an alias for `Reg<PSC_SPEC>`
124pub type PSC = crate::Reg<psc::PSC_SPEC>;
125///desc PSC
126pub mod psc;
127///ARR (rw) register accessor: an alias for `Reg<ARR_SPEC>`
128pub type ARR = crate::Reg<arr::ARR_SPEC>;
129///desc ARR
130pub mod arr;
131///RCR (rw) register accessor: an alias for `Reg<RCR_SPEC>`
132pub type RCR = crate::Reg<rcr::RCR_SPEC>;
133///desc RCR
134pub mod rcr;
135///CCR (rw) register accessor: an alias for `Reg<CCR_SPEC>`
136pub type CCR = crate::Reg<ccr::CCR_SPEC>;
137///desc CCR%s
138pub mod ccr;
139///BDTR (rw) register accessor: an alias for `Reg<BDTR_SPEC>`
140pub type BDTR = crate::Reg<bdtr::BDTR_SPEC>;
141///desc BDTR
142pub mod bdtr;
py32f0/py32f002b/tim1.rs

py32f0/py32f002b/
tim1.rs
