py32f0/py32f002b/rcc/
cier.rs

1///Register `CIER` reader
2pub struct R(crate::R<CIER_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CIER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CIER_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CIER_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CIER` writer
17pub struct W(crate::W<CIER_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CIER_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CIER_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CIER_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `LSIRDYIE` reader - LSI ready interrupt enable
38pub type LSIRDYIE_R = crate::BitReader<LSIRDYIE_A>;
39/**LSI ready interrupt enable
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum LSIRDYIE_A {
44    ///0: Ready interrupt disabled
45    Disabled = 0,
46    ///1: Ready interrupt enabled
47    Enabled = 1,
48}
49impl From<LSIRDYIE_A> for bool {
50    #[inline(always)]
51    fn from(variant: LSIRDYIE_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl LSIRDYIE_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> LSIRDYIE_A {
59        match self.bits {
60            false => LSIRDYIE_A::Disabled,
61            true => LSIRDYIE_A::Enabled,
62        }
63    }
64    ///Checks if the value of the field is `Disabled`
65    #[inline(always)]
66    pub fn is_disabled(&self) -> bool {
67        *self == LSIRDYIE_A::Disabled
68    }
69    ///Checks if the value of the field is `Enabled`
70    #[inline(always)]
71    pub fn is_enabled(&self) -> bool {
72        *self == LSIRDYIE_A::Enabled
73    }
74}
75///Field `LSIRDYIE` writer - LSI ready interrupt enable
76pub type LSIRDYIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CIER_SPEC, LSIRDYIE_A, O>;
77impl<'a, const O: u8> LSIRDYIE_W<'a, O> {
78    ///Ready interrupt disabled
79    #[inline(always)]
80    pub fn disabled(self) -> &'a mut W {
81        self.variant(LSIRDYIE_A::Disabled)
82    }
83    ///Ready interrupt enabled
84    #[inline(always)]
85    pub fn enabled(self) -> &'a mut W {
86        self.variant(LSIRDYIE_A::Enabled)
87    }
88}
89///Field `LSERDYIE` reader - LSE ready interrupt enable
90pub use LSIRDYIE_R as LSERDYIE_R;
91///Field `HSIRDYIE` reader - HSI ready interrupt enable
92pub use LSIRDYIE_R as HSIRDYIE_R;
93///Field `LSERDYIE` writer - LSE ready interrupt enable
94pub use LSIRDYIE_W as LSERDYIE_W;
95///Field `HSIRDYIE` writer - HSI ready interrupt enable
96pub use LSIRDYIE_W as HSIRDYIE_W;
97impl R {
98    ///Bit 0 - LSI ready interrupt enable
99    #[inline(always)]
100    pub fn lsirdyie(&self) -> LSIRDYIE_R {
101        LSIRDYIE_R::new((self.bits & 1) != 0)
102    }
103    ///Bit 1 - LSE ready interrupt enable
104    #[inline(always)]
105    pub fn lserdyie(&self) -> LSERDYIE_R {
106        LSERDYIE_R::new(((self.bits >> 1) & 1) != 0)
107    }
108    ///Bit 3 - HSI ready interrupt enable
109    #[inline(always)]
110    pub fn hsirdyie(&self) -> HSIRDYIE_R {
111        HSIRDYIE_R::new(((self.bits >> 3) & 1) != 0)
112    }
113}
114impl W {
115    ///Bit 0 - LSI ready interrupt enable
116    #[inline(always)]
117    #[must_use]
118    pub fn lsirdyie(&mut self) -> LSIRDYIE_W<0> {
119        LSIRDYIE_W::new(self)
120    }
121    ///Bit 1 - LSE ready interrupt enable
122    #[inline(always)]
123    #[must_use]
124    pub fn lserdyie(&mut self) -> LSERDYIE_W<1> {
125        LSERDYIE_W::new(self)
126    }
127    ///Bit 3 - HSI ready interrupt enable
128    #[inline(always)]
129    #[must_use]
130    pub fn hsirdyie(&mut self) -> HSIRDYIE_W<3> {
131        HSIRDYIE_W::new(self)
132    }
133    ///Writes raw bits to the register.
134    #[inline(always)]
135    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
136        self.0.bits(bits);
137        self
138    }
139}
140/**Clock interrupt enable register
141
142This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
143
144For information about available fields see [cier](index.html) module*/
145pub struct CIER_SPEC;
146impl crate::RegisterSpec for CIER_SPEC {
147    type Ux = u32;
148}
149///`read()` method returns [cier::R](R) reader structure
150impl crate::Readable for CIER_SPEC {
151    type Reader = R;
152}
153///`write(|w| ..)` method takes [cier::W](W) writer structure
154impl crate::Writable for CIER_SPEC {
155    type Writer = W;
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
158}
159///`reset()` method sets CIER to value 0
160impl crate::Resettable for CIER_SPEC {
161    const RESET_VALUE: Self::Ux = 0;
162}
py32f0/py32f002b/rcc/cier.rs

py32f0/py32f002b/rcc/
cier.rs
