py32f0/py32f002b/gpioc/
moder.rs

1///Register `MODER` reader
2pub struct R(crate::R<MODER_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MODER_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MODER_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MODER_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `MODER` writer
17pub struct W(crate::W<MODER_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MODER_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MODER_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MODER_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `MODE0` reader - Port x configuration bits (y = 0..15)
38pub type MODE0_R = crate::FieldReader<u8, MODE0_A>;
39/**Port x configuration bits (y = 0..15)
40
41Value on reset: 3*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u8)]
44pub enum MODE0_A {
45    ///0: Input mode
46    Input = 0,
47    ///1: General purpose output mode
48    Output = 1,
49    ///2: Alternate function mode
50    Alternate = 2,
51    ///3: Analog mode
52    Analog = 3,
53}
54impl From<MODE0_A> for u8 {
55    #[inline(always)]
56    fn from(variant: MODE0_A) -> Self {
57        variant as _
58    }
59}
60impl MODE0_R {
61    ///Get enumerated values variant
62    #[inline(always)]
63    pub fn variant(&self) -> MODE0_A {
64        match self.bits {
65            0 => MODE0_A::Input,
66            1 => MODE0_A::Output,
67            2 => MODE0_A::Alternate,
68            3 => MODE0_A::Analog,
69            _ => unreachable!(),
70        }
71    }
72    ///Checks if the value of the field is `Input`
73    #[inline(always)]
74    pub fn is_input(&self) -> bool {
75        *self == MODE0_A::Input
76    }
77    ///Checks if the value of the field is `Output`
78    #[inline(always)]
79    pub fn is_output(&self) -> bool {
80        *self == MODE0_A::Output
81    }
82    ///Checks if the value of the field is `Alternate`
83    #[inline(always)]
84    pub fn is_alternate(&self) -> bool {
85        *self == MODE0_A::Alternate
86    }
87    ///Checks if the value of the field is `Analog`
88    #[inline(always)]
89    pub fn is_analog(&self) -> bool {
90        *self == MODE0_A::Analog
91    }
92}
93///Field `MODE0` writer - Port x configuration bits (y = 0..15)
94pub type MODE0_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, MODER_SPEC, u8, MODE0_A, 2, O>;
95impl<'a, const O: u8> MODE0_W<'a, O> {
96    ///Input mode
97    #[inline(always)]
98    pub fn input(self) -> &'a mut W {
99        self.variant(MODE0_A::Input)
100    }
101    ///General purpose output mode
102    #[inline(always)]
103    pub fn output(self) -> &'a mut W {
104        self.variant(MODE0_A::Output)
105    }
106    ///Alternate function mode
107    #[inline(always)]
108    pub fn alternate(self) -> &'a mut W {
109        self.variant(MODE0_A::Alternate)
110    }
111    ///Analog mode
112    #[inline(always)]
113    pub fn analog(self) -> &'a mut W {
114        self.variant(MODE0_A::Analog)
115    }
116}
117///Field `MODE1` reader - Port x configuration bits (y = 0..15)
118pub use MODE0_R as MODE1_R;
119///Field `MODE1` writer - Port x configuration bits (y = 0..15)
120pub use MODE0_W as MODE1_W;
121impl R {
122    ///Bits 0:1 - Port x configuration bits (y = 0..15)
123    #[inline(always)]
124    pub fn mode0(&self) -> MODE0_R {
125        MODE0_R::new((self.bits & 3) as u8)
126    }
127    ///Bits 2:3 - Port x configuration bits (y = 0..15)
128    #[inline(always)]
129    pub fn mode1(&self) -> MODE1_R {
130        MODE1_R::new(((self.bits >> 2) & 3) as u8)
131    }
132}
133impl W {
134    ///Bits 0:1 - Port x configuration bits (y = 0..15)
135    #[inline(always)]
136    #[must_use]
137    pub fn mode0(&mut self) -> MODE0_W<0> {
138        MODE0_W::new(self)
139    }
140    ///Bits 2:3 - Port x configuration bits (y = 0..15)
141    #[inline(always)]
142    #[must_use]
143    pub fn mode1(&mut self) -> MODE1_W<2> {
144        MODE1_W::new(self)
145    }
146    ///Writes raw bits to the register.
147    #[inline(always)]
148    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
149        self.0.bits(bits);
150        self
151    }
152}
153/**GPIO port mode register
154
155This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
156
157For information about available fields see [moder](index.html) module*/
158pub struct MODER_SPEC;
159impl crate::RegisterSpec for MODER_SPEC {
160    type Ux = u32;
161}
162///`read()` method returns [moder::R](R) reader structure
163impl crate::Readable for MODER_SPEC {
164    type Reader = R;
165}
166///`write(|w| ..)` method takes [moder::W](W) writer structure
167impl crate::Writable for MODER_SPEC {
168    type Writer = W;
169    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
170    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
171}
172///`reset()` method sets MODER to value 0xebff_ffff
173impl crate::Resettable for MODER_SPEC {
174    const RESET_VALUE: Self::Ux = 0xebff_ffff;
175}
py32f0/py32f002b/gpioc/moder.rs

py32f0/py32f002b/gpioc/
moder.rs
