py32f0/py32f002b/gpioa/
brr.rs

1///Register `BRR` writer
2pub struct W(crate::W<BRR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<BRR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<BRR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<BRR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22/**Port Reset bit
23
24Value on reset: 0*/
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum BR0W_AW {
27    ///0: No action on the corresponding ODx bit
28    NoAction = 0,
29    ///1: Reset the ODx bit
30    Reset = 1,
31}
32impl From<BR0W_AW> for bool {
33    #[inline(always)]
34    fn from(variant: BR0W_AW) -> Self {
35        variant as u8 != 0
36    }
37}
38///Field `BR0` writer - Port Reset bit
39pub type BR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, BRR_SPEC, BR0W_AW, O>;
40impl<'a, const O: u8> BR0_W<'a, O> {
41    ///No action on the corresponding ODx bit
42    #[inline(always)]
43    pub fn no_action(self) -> &'a mut W {
44        self.variant(BR0W_AW::NoAction)
45    }
46    ///Reset the ODx bit
47    #[inline(always)]
48    pub fn reset(self) -> &'a mut W {
49        self.variant(BR0W_AW::Reset)
50    }
51}
52///Field `BR1` writer - Port Reset bit
53pub use BR0_W as BR1_W;
54///Field `BR2` writer - Port Reset bit
55pub use BR0_W as BR2_W;
56///Field `BR3` writer - Port Reset bit
57pub use BR0_W as BR3_W;
58///Field `BR4` writer - Port Reset bit
59pub use BR0_W as BR4_W;
60///Field `BR5` writer - Port Reset bit
61pub use BR0_W as BR5_W;
62///Field `BR6` writer - Port Reset bit
63pub use BR0_W as BR6_W;
64///Field `BR7` writer - Port Reset bit
65pub use BR0_W as BR7_W;
66impl W {
67    ///Bit 0 - Port Reset bit
68    #[inline(always)]
69    #[must_use]
70    pub fn br0(&mut self) -> BR0_W<0> {
71        BR0_W::new(self)
72    }
73    ///Bit 1 - Port Reset bit
74    #[inline(always)]
75    #[must_use]
76    pub fn br1(&mut self) -> BR1_W<1> {
77        BR1_W::new(self)
78    }
79    ///Bit 2 - Port Reset bit
80    #[inline(always)]
81    #[must_use]
82    pub fn br2(&mut self) -> BR2_W<2> {
83        BR2_W::new(self)
84    }
85    ///Bit 3 - Port Reset bit
86    #[inline(always)]
87    #[must_use]
88    pub fn br3(&mut self) -> BR3_W<3> {
89        BR3_W::new(self)
90    }
91    ///Bit 4 - Port Reset bit
92    #[inline(always)]
93    #[must_use]
94    pub fn br4(&mut self) -> BR4_W<4> {
95        BR4_W::new(self)
96    }
97    ///Bit 5 - Port Reset bit
98    #[inline(always)]
99    #[must_use]
100    pub fn br5(&mut self) -> BR5_W<5> {
101        BR5_W::new(self)
102    }
103    ///Bit 6 - Port Reset bit
104    #[inline(always)]
105    #[must_use]
106    pub fn br6(&mut self) -> BR6_W<6> {
107        BR6_W::new(self)
108    }
109    ///Bit 7 - Port Reset bit
110    #[inline(always)]
111    #[must_use]
112    pub fn br7(&mut self) -> BR7_W<7> {
113        BR7_W::new(self)
114    }
115    ///Writes raw bits to the register.
116    #[inline(always)]
117    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
118        self.0.bits(bits);
119        self
120    }
121}
122/**port bit reset register
123
124This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
125
126For information about available fields see [brr](index.html) module*/
127pub struct BRR_SPEC;
128impl crate::RegisterSpec for BRR_SPEC {
129    type Ux = u32;
130}
131///`write(|w| ..)` method takes [brr::W](W) writer structure
132impl crate::Writable for BRR_SPEC {
133    type Writer = W;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136}
137///`reset()` method sets BRR to value 0
138impl crate::Resettable for BRR_SPEC {
139    const RESET_VALUE: Self::Ux = 0;
140}
py32f0/py32f002b/gpioa/brr.rs

py32f0/py32f002b/gpioa/
brr.rs
