py32f0/py32f002a/tim16/
egr.rs

1///Register `EGR` writer
2pub struct W(crate::W<EGR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<EGR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<EGR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<EGR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22/**Update generation
23
24Value on reset: 0*/
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum UGW_AW {
27    ///1: Re-initializes the timer counter and generates an update of the registers.
28    Trigger = 1,
29}
30impl From<UGW_AW> for bool {
31    #[inline(always)]
32    fn from(variant: UGW_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36///Field `UG` writer - Update generation
37pub type UG_W<'a, const O: u8> = crate::BitWriter<'a, u32, EGR_SPEC, UGW_AW, O>;
38impl<'a, const O: u8> UG_W<'a, O> {
39    ///Re-initializes the timer counter and generates an update of the registers.
40    #[inline(always)]
41    pub fn trigger(self) -> &'a mut W {
42        self.variant(UGW_AW::Trigger)
43    }
44}
45impl W {
46    ///Bit 0 - Update generation
47    #[inline(always)]
48    #[must_use]
49    pub fn ug(&mut self) -> UG_W<0> {
50        UG_W::new(self)
51    }
52    ///Writes raw bits to the register.
53    #[inline(always)]
54    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
55        self.0.bits(bits);
56        self
57    }
58}
59/**event generation register
60
61This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
62
63For information about available fields see [egr](index.html) module*/
64pub struct EGR_SPEC;
65impl crate::RegisterSpec for EGR_SPEC {
66    type Ux = u32;
67}
68///`write(|w| ..)` method takes [egr::W](W) writer structure
69impl crate::Writable for EGR_SPEC {
70    type Writer = W;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
73}
74///`reset()` method sets EGR to value 0
75impl crate::Resettable for EGR_SPEC {
76    const RESET_VALUE: Self::Ux = 0;
77}
py32f0/py32f002a/tim16/egr.rs

py32f0/py32f002a/tim16/
egr.rs
