py32f0/py32f002a/tim16/
cr1.rs

1///Register `CR1` reader
2pub struct R(crate::R<CR1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CR1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CR1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CR1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CR1` writer
17pub struct W(crate::W<CR1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CR1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CR1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CR1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CEN` reader - Counter enable
38pub type CEN_R = crate::BitReader<CEN_A>;
39/**Counter enable
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum CEN_A {
44    ///0: Counter disabled
45    Disabled = 0,
46    ///1: Counter enabled
47    Enabled = 1,
48}
49impl From<CEN_A> for bool {
50    #[inline(always)]
51    fn from(variant: CEN_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl CEN_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> CEN_A {
59        match self.bits {
60            false => CEN_A::Disabled,
61            true => CEN_A::Enabled,
62        }
63    }
64    ///Checks if the value of the field is `Disabled`
65    #[inline(always)]
66    pub fn is_disabled(&self) -> bool {
67        *self == CEN_A::Disabled
68    }
69    ///Checks if the value of the field is `Enabled`
70    #[inline(always)]
71    pub fn is_enabled(&self) -> bool {
72        *self == CEN_A::Enabled
73    }
74}
75///Field `CEN` writer - Counter enable
76pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, CEN_A, O>;
77impl<'a, const O: u8> CEN_W<'a, O> {
78    ///Counter disabled
79    #[inline(always)]
80    pub fn disabled(self) -> &'a mut W {
81        self.variant(CEN_A::Disabled)
82    }
83    ///Counter enabled
84    #[inline(always)]
85    pub fn enabled(self) -> &'a mut W {
86        self.variant(CEN_A::Enabled)
87    }
88}
89///Field `UDIS` reader - Update disable
90pub type UDIS_R = crate::BitReader<UDIS_A>;
91/**Update disable
92
93Value on reset: 0*/
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum UDIS_A {
96    ///0: Update event enabled
97    Enabled = 0,
98    ///1: Update event disabled
99    Disabled = 1,
100}
101impl From<UDIS_A> for bool {
102    #[inline(always)]
103    fn from(variant: UDIS_A) -> Self {
104        variant as u8 != 0
105    }
106}
107impl UDIS_R {
108    ///Get enumerated values variant
109    #[inline(always)]
110    pub fn variant(&self) -> UDIS_A {
111        match self.bits {
112            false => UDIS_A::Enabled,
113            true => UDIS_A::Disabled,
114        }
115    }
116    ///Checks if the value of the field is `Enabled`
117    #[inline(always)]
118    pub fn is_enabled(&self) -> bool {
119        *self == UDIS_A::Enabled
120    }
121    ///Checks if the value of the field is `Disabled`
122    #[inline(always)]
123    pub fn is_disabled(&self) -> bool {
124        *self == UDIS_A::Disabled
125    }
126}
127///Field `UDIS` writer - Update disable
128pub type UDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, UDIS_A, O>;
129impl<'a, const O: u8> UDIS_W<'a, O> {
130    ///Update event enabled
131    #[inline(always)]
132    pub fn enabled(self) -> &'a mut W {
133        self.variant(UDIS_A::Enabled)
134    }
135    ///Update event disabled
136    #[inline(always)]
137    pub fn disabled(self) -> &'a mut W {
138        self.variant(UDIS_A::Disabled)
139    }
140}
141///Field `URS` reader - Update request source
142pub type URS_R = crate::BitReader<URS_A>;
143/**Update request source
144
145Value on reset: 0*/
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum URS_A {
148    ///0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
149    AnyEvent = 0,
150    ///1: Only counter overflow/underflow generates an update interrupt or DMA request
151    CounterOnly = 1,
152}
153impl From<URS_A> for bool {
154    #[inline(always)]
155    fn from(variant: URS_A) -> Self {
156        variant as u8 != 0
157    }
158}
159impl URS_R {
160    ///Get enumerated values variant
161    #[inline(always)]
162    pub fn variant(&self) -> URS_A {
163        match self.bits {
164            false => URS_A::AnyEvent,
165            true => URS_A::CounterOnly,
166        }
167    }
168    ///Checks if the value of the field is `AnyEvent`
169    #[inline(always)]
170    pub fn is_any_event(&self) -> bool {
171        *self == URS_A::AnyEvent
172    }
173    ///Checks if the value of the field is `CounterOnly`
174    #[inline(always)]
175    pub fn is_counter_only(&self) -> bool {
176        *self == URS_A::CounterOnly
177    }
178}
179///Field `URS` writer - Update request source
180pub type URS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, URS_A, O>;
181impl<'a, const O: u8> URS_W<'a, O> {
182    ///Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
183    #[inline(always)]
184    pub fn any_event(self) -> &'a mut W {
185        self.variant(URS_A::AnyEvent)
186    }
187    ///Only counter overflow/underflow generates an update interrupt or DMA request
188    #[inline(always)]
189    pub fn counter_only(self) -> &'a mut W {
190        self.variant(URS_A::CounterOnly)
191    }
192}
193///Field `OPM` reader - One pulse mode
194pub type OPM_R = crate::BitReader<bool>;
195///Field `OPM` writer - One pulse mode
196pub type OPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, bool, O>;
197///Field `ARPE` reader - Auto-reload preload enable
198pub type ARPE_R = crate::BitReader<ARPE_A>;
199/**Auto-reload preload enable
200
201Value on reset: 0*/
202#[derive(Clone, Copy, Debug, PartialEq, Eq)]
203pub enum ARPE_A {
204    ///0: TIMx_APRR register is not buffered
205    Disabled = 0,
206    ///1: TIMx_APRR register is buffered
207    Enabled = 1,
208}
209impl From<ARPE_A> for bool {
210    #[inline(always)]
211    fn from(variant: ARPE_A) -> Self {
212        variant as u8 != 0
213    }
214}
215impl ARPE_R {
216    ///Get enumerated values variant
217    #[inline(always)]
218    pub fn variant(&self) -> ARPE_A {
219        match self.bits {
220            false => ARPE_A::Disabled,
221            true => ARPE_A::Enabled,
222        }
223    }
224    ///Checks if the value of the field is `Disabled`
225    #[inline(always)]
226    pub fn is_disabled(&self) -> bool {
227        *self == ARPE_A::Disabled
228    }
229    ///Checks if the value of the field is `Enabled`
230    #[inline(always)]
231    pub fn is_enabled(&self) -> bool {
232        *self == ARPE_A::Enabled
233    }
234}
235///Field `ARPE` writer - Auto-reload preload enable
236pub type ARPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, ARPE_A, O>;
237impl<'a, const O: u8> ARPE_W<'a, O> {
238    ///TIMx_APRR register is not buffered
239    #[inline(always)]
240    pub fn disabled(self) -> &'a mut W {
241        self.variant(ARPE_A::Disabled)
242    }
243    ///TIMx_APRR register is buffered
244    #[inline(always)]
245    pub fn enabled(self) -> &'a mut W {
246        self.variant(ARPE_A::Enabled)
247    }
248}
249///Field `CKD` reader - Prescaler factor
250pub type CKD_R = crate::FieldReader<u8, u8>;
251///Field `CKD` writer - Prescaler factor
252pub type CKD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CR1_SPEC, u8, u8, 2, O>;
253impl R {
254    ///Bit 0 - Counter enable
255    #[inline(always)]
256    pub fn cen(&self) -> CEN_R {
257        CEN_R::new((self.bits & 1) != 0)
258    }
259    ///Bit 1 - Update disable
260    #[inline(always)]
261    pub fn udis(&self) -> UDIS_R {
262        UDIS_R::new(((self.bits >> 1) & 1) != 0)
263    }
264    ///Bit 2 - Update request source
265    #[inline(always)]
266    pub fn urs(&self) -> URS_R {
267        URS_R::new(((self.bits >> 2) & 1) != 0)
268    }
269    ///Bit 3 - One pulse mode
270    #[inline(always)]
271    pub fn opm(&self) -> OPM_R {
272        OPM_R::new(((self.bits >> 3) & 1) != 0)
273    }
274    ///Bit 7 - Auto-reload preload enable
275    #[inline(always)]
276    pub fn arpe(&self) -> ARPE_R {
277        ARPE_R::new(((self.bits >> 7) & 1) != 0)
278    }
279    ///Bits 8:9 - Prescaler factor
280    #[inline(always)]
281    pub fn ckd(&self) -> CKD_R {
282        CKD_R::new(((self.bits >> 8) & 3) as u8)
283    }
284}
285impl W {
286    ///Bit 0 - Counter enable
287    #[inline(always)]
288    #[must_use]
289    pub fn cen(&mut self) -> CEN_W<0> {
290        CEN_W::new(self)
291    }
292    ///Bit 1 - Update disable
293    #[inline(always)]
294    #[must_use]
295    pub fn udis(&mut self) -> UDIS_W<1> {
296        UDIS_W::new(self)
297    }
298    ///Bit 2 - Update request source
299    #[inline(always)]
300    #[must_use]
301    pub fn urs(&mut self) -> URS_W<2> {
302        URS_W::new(self)
303    }
304    ///Bit 3 - One pulse mode
305    #[inline(always)]
306    #[must_use]
307    pub fn opm(&mut self) -> OPM_W<3> {
308        OPM_W::new(self)
309    }
310    ///Bit 7 - Auto-reload preload enable
311    #[inline(always)]
312    #[must_use]
313    pub fn arpe(&mut self) -> ARPE_W<7> {
314        ARPE_W::new(self)
315    }
316    ///Bits 8:9 - Prescaler factor
317    #[inline(always)]
318    #[must_use]
319    pub fn ckd(&mut self) -> CKD_W<8> {
320        CKD_W::new(self)
321    }
322    ///Writes raw bits to the register.
323    #[inline(always)]
324    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
325        self.0.bits(bits);
326        self
327    }
328}
329/**TIM16 control register1
330
331This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
332
333For information about available fields see [cr1](index.html) module*/
334pub struct CR1_SPEC;
335impl crate::RegisterSpec for CR1_SPEC {
336    type Ux = u32;
337}
338///`read()` method returns [cr1::R](R) reader structure
339impl crate::Readable for CR1_SPEC {
340    type Reader = R;
341}
342///`write(|w| ..)` method takes [cr1::W](W) writer structure
343impl crate::Writable for CR1_SPEC {
344    type Writer = W;
345    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
346    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
347}
348///`reset()` method sets CR1 to value 0
349impl crate::Resettable for CR1_SPEC {
350    const RESET_VALUE: Self::Ux = 0;
351}
py32f0/py32f002a/tim16/cr1.rs

py32f0/py32f002a/tim16/
cr1.rs
