py32f0/py32f030/tim14/
ccmr1_output.rs

1///Register `CCMR1_Output` reader
2pub struct R(crate::R<CCMR1_OUTPUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCMR1_OUTPUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCMR1_OUTPUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCMR1_OUTPUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CCMR1_Output` writer
17pub struct W(crate::W<CCMR1_OUTPUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCMR1_OUTPUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCMR1_OUTPUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCMR1_OUTPUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CC1S` reader - Capture/Compare 1 selection
38pub type CC1S_R = crate::FieldReader<u8, CC1S_A>;
39/**Capture/Compare 1 selection
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u8)]
44pub enum CC1S_A {
45    ///0: CC1 channel is configured as output
46    Output = 0,
47}
48impl From<CC1S_A> for u8 {
49    #[inline(always)]
50    fn from(variant: CC1S_A) -> Self {
51        variant as _
52    }
53}
54impl CC1S_R {
55    ///Get enumerated values variant
56    #[inline(always)]
57    pub fn variant(&self) -> Option<CC1S_A> {
58        match self.bits {
59            0 => Some(CC1S_A::Output),
60            _ => None,
61        }
62    }
63    ///Checks if the value of the field is `Output`
64    #[inline(always)]
65    pub fn is_output(&self) -> bool {
66        *self == CC1S_A::Output
67    }
68}
69///Field `CC1S` writer - Capture/Compare 1 selection
70pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, CC1S_A, 2, O>;
71impl<'a, const O: u8> CC1S_W<'a, O> {
72    ///CC1 channel is configured as output
73    #[inline(always)]
74    pub fn output(self) -> &'a mut W {
75        self.variant(CC1S_A::Output)
76    }
77}
78///Field `OC1FE` reader - Output Compare 1 fast enable
79pub type OC1FE_R = crate::BitReader<bool>;
80///Field `OC1FE` writer - Output Compare 1 fast enable
81pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
82///Field `OC1PE` reader - Output Compare 1 preload enable
83pub type OC1PE_R = crate::BitReader<OC1PE_A>;
84/**Output Compare 1 preload enable
85
86Value on reset: 0*/
87#[derive(Clone, Copy, Debug, PartialEq, Eq)]
88pub enum OC1PE_A {
89    ///0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
90    Disabled = 0,
91    ///1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
92    Enabled = 1,
93}
94impl From<OC1PE_A> for bool {
95    #[inline(always)]
96    fn from(variant: OC1PE_A) -> Self {
97        variant as u8 != 0
98    }
99}
100impl OC1PE_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub fn variant(&self) -> OC1PE_A {
104        match self.bits {
105            false => OC1PE_A::Disabled,
106            true => OC1PE_A::Enabled,
107        }
108    }
109    ///Checks if the value of the field is `Disabled`
110    #[inline(always)]
111    pub fn is_disabled(&self) -> bool {
112        *self == OC1PE_A::Disabled
113    }
114    ///Checks if the value of the field is `Enabled`
115    #[inline(always)]
116    pub fn is_enabled(&self) -> bool {
117        *self == OC1PE_A::Enabled
118    }
119}
120///Field `OC1PE` writer - Output Compare 1 preload enable
121pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, OC1PE_A, O>;
122impl<'a, const O: u8> OC1PE_W<'a, O> {
123    ///Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately
124    #[inline(always)]
125    pub fn disabled(self) -> &'a mut W {
126        self.variant(OC1PE_A::Disabled)
127    }
128    ///Preload register on CCR1 enabled. Preload value is loaded into active register on each update event
129    #[inline(always)]
130    pub fn enabled(self) -> &'a mut W {
131        self.variant(OC1PE_A::Enabled)
132    }
133}
134///Field `OC1M` reader - Output Compare 1 mode
135pub type OC1M_R = crate::FieldReader<u8, OC1M_A>;
136/**Output Compare 1 mode
137
138Value on reset: 0*/
139#[derive(Clone, Copy, Debug, PartialEq, Eq)]
140#[repr(u8)]
141pub enum OC1M_A {
142    ///0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
143    Frozen = 0,
144    ///1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
145    ActiveOnMatch = 1,
146    ///2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
147    InactiveOnMatch = 2,
148    ///3: OCyREF toggles when TIMx_CNT=TIMx_CCRy
149    Toggle = 3,
150    ///4: OCyREF is forced low
151    ForceInactive = 4,
152    ///5: OCyREF is forced high
153    ForceActive = 5,
154    ///6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
155    PwmMode1 = 6,
156    ///7: Inversely to PwmMode1
157    PwmMode2 = 7,
158}
159impl From<OC1M_A> for u8 {
160    #[inline(always)]
161    fn from(variant: OC1M_A) -> Self {
162        variant as _
163    }
164}
165impl OC1M_R {
166    ///Get enumerated values variant
167    #[inline(always)]
168    pub fn variant(&self) -> OC1M_A {
169        match self.bits {
170            0 => OC1M_A::Frozen,
171            1 => OC1M_A::ActiveOnMatch,
172            2 => OC1M_A::InactiveOnMatch,
173            3 => OC1M_A::Toggle,
174            4 => OC1M_A::ForceInactive,
175            5 => OC1M_A::ForceActive,
176            6 => OC1M_A::PwmMode1,
177            7 => OC1M_A::PwmMode2,
178            _ => unreachable!(),
179        }
180    }
181    ///Checks if the value of the field is `Frozen`
182    #[inline(always)]
183    pub fn is_frozen(&self) -> bool {
184        *self == OC1M_A::Frozen
185    }
186    ///Checks if the value of the field is `ActiveOnMatch`
187    #[inline(always)]
188    pub fn is_active_on_match(&self) -> bool {
189        *self == OC1M_A::ActiveOnMatch
190    }
191    ///Checks if the value of the field is `InactiveOnMatch`
192    #[inline(always)]
193    pub fn is_inactive_on_match(&self) -> bool {
194        *self == OC1M_A::InactiveOnMatch
195    }
196    ///Checks if the value of the field is `Toggle`
197    #[inline(always)]
198    pub fn is_toggle(&self) -> bool {
199        *self == OC1M_A::Toggle
200    }
201    ///Checks if the value of the field is `ForceInactive`
202    #[inline(always)]
203    pub fn is_force_inactive(&self) -> bool {
204        *self == OC1M_A::ForceInactive
205    }
206    ///Checks if the value of the field is `ForceActive`
207    #[inline(always)]
208    pub fn is_force_active(&self) -> bool {
209        *self == OC1M_A::ForceActive
210    }
211    ///Checks if the value of the field is `PwmMode1`
212    #[inline(always)]
213    pub fn is_pwm_mode1(&self) -> bool {
214        *self == OC1M_A::PwmMode1
215    }
216    ///Checks if the value of the field is `PwmMode2`
217    #[inline(always)]
218    pub fn is_pwm_mode2(&self) -> bool {
219        *self == OC1M_A::PwmMode2
220    }
221}
222///Field `OC1M` writer - Output Compare 1 mode
223pub type OC1M_W<'a, const O: u8> =
224    crate::FieldWriterSafe<'a, u32, CCMR1_OUTPUT_SPEC, u8, OC1M_A, 3, O>;
225impl<'a, const O: u8> OC1M_W<'a, O> {
226    ///The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
227    #[inline(always)]
228    pub fn frozen(self) -> &'a mut W {
229        self.variant(OC1M_A::Frozen)
230    }
231    ///Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
232    #[inline(always)]
233    pub fn active_on_match(self) -> &'a mut W {
234        self.variant(OC1M_A::ActiveOnMatch)
235    }
236    ///Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
237    #[inline(always)]
238    pub fn inactive_on_match(self) -> &'a mut W {
239        self.variant(OC1M_A::InactiveOnMatch)
240    }
241    ///OCyREF toggles when TIMx_CNT=TIMx_CCRy
242    #[inline(always)]
243    pub fn toggle(self) -> &'a mut W {
244        self.variant(OC1M_A::Toggle)
245    }
246    ///OCyREF is forced low
247    #[inline(always)]
248    pub fn force_inactive(self) -> &'a mut W {
249        self.variant(OC1M_A::ForceInactive)
250    }
251    ///OCyREF is forced high
252    #[inline(always)]
253    pub fn force_active(self) -> &'a mut W {
254        self.variant(OC1M_A::ForceActive)
255    }
256    ///In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
257    #[inline(always)]
258    pub fn pwm_mode1(self) -> &'a mut W {
259        self.variant(OC1M_A::PwmMode1)
260    }
261    ///Inversely to PwmMode1
262    #[inline(always)]
263    pub fn pwm_mode2(self) -> &'a mut W {
264        self.variant(OC1M_A::PwmMode2)
265    }
266}
267impl R {
268    ///Bits 0:1 - Capture/Compare 1 selection
269    #[inline(always)]
270    pub fn cc1s(&self) -> CC1S_R {
271        CC1S_R::new((self.bits & 3) as u8)
272    }
273    ///Bit 2 - Output Compare 1 fast enable
274    #[inline(always)]
275    pub fn oc1fe(&self) -> OC1FE_R {
276        OC1FE_R::new(((self.bits >> 2) & 1) != 0)
277    }
278    ///Bit 3 - Output Compare 1 preload enable
279    #[inline(always)]
280    pub fn oc1pe(&self) -> OC1PE_R {
281        OC1PE_R::new(((self.bits >> 3) & 1) != 0)
282    }
283    ///Bits 4:6 - Output Compare 1 mode
284    #[inline(always)]
285    pub fn oc1m(&self) -> OC1M_R {
286        OC1M_R::new(((self.bits >> 4) & 7) as u8)
287    }
288}
289impl W {
290    ///Bits 0:1 - Capture/Compare 1 selection
291    #[inline(always)]
292    #[must_use]
293    pub fn cc1s(&mut self) -> CC1S_W<0> {
294        CC1S_W::new(self)
295    }
296    ///Bit 2 - Output Compare 1 fast enable
297    #[inline(always)]
298    #[must_use]
299    pub fn oc1fe(&mut self) -> OC1FE_W<2> {
300        OC1FE_W::new(self)
301    }
302    ///Bit 3 - Output Compare 1 preload enable
303    #[inline(always)]
304    #[must_use]
305    pub fn oc1pe(&mut self) -> OC1PE_W<3> {
306        OC1PE_W::new(self)
307    }
308    ///Bits 4:6 - Output Compare 1 mode
309    #[inline(always)]
310    #[must_use]
311    pub fn oc1m(&mut self) -> OC1M_W<4> {
312        OC1M_W::new(self)
313    }
314    ///Writes raw bits to the register.
315    #[inline(always)]
316    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
317        self.0.bits(bits);
318        self
319    }
320}
321/**capture/compare mode register (output mode)
322
323This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
324
325For information about available fields see [ccmr1_output](index.html) module*/
326pub struct CCMR1_OUTPUT_SPEC;
327impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC {
328    type Ux = u32;
329}
330///`read()` method returns [ccmr1_output::R](R) reader structure
331impl crate::Readable for CCMR1_OUTPUT_SPEC {
332    type Reader = R;
333}
334///`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure
335impl crate::Writable for CCMR1_OUTPUT_SPEC {
336    type Writer = W;
337    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
338    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
339}
340///`reset()` method sets CCMR1_Output to value 0
341impl crate::Resettable for CCMR1_OUTPUT_SPEC {
342    const RESET_VALUE: Self::Ux = 0;
343}
py32f0/py32f030/tim14/ccmr1_output.rs

py32f0/py32f030/tim14/
ccmr1_output.rs
