py32f0/py32f030/tim1/
ccmr2_input.rs

1///Register `CCMR2_Input` reader
2pub struct R(crate::R<CCMR2_INPUT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CCMR2_INPUT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CCMR2_INPUT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CCMR2_INPUT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CCMR2_Input` writer
17pub struct W(crate::W<CCMR2_INPUT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CCMR2_INPUT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CCMR2_INPUT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CCMR2_INPUT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `CC3S` reader - Capture/compare 3 selection
38pub type CC3S_R = crate::FieldReader<u8, CC3S_A>;
39/**Capture/compare 3 selection
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u8)]
44pub enum CC3S_A {
45    ///0: CC3 channel is configured as output
46    Output = 0,
47    ///1: CC3 channel is configured as input, IC3 is mapped on TI3
48    Ti3 = 1,
49    ///2: CC3 channel is configured as input, IC3 is mapped on TI4
50    Ti4 = 2,
51    ///3: CC3 channel is configured as input, IC3 is mapped on TRC
52    Trc = 3,
53}
54impl From<CC3S_A> for u8 {
55    #[inline(always)]
56    fn from(variant: CC3S_A) -> Self {
57        variant as _
58    }
59}
60impl CC3S_R {
61    ///Get enumerated values variant
62    #[inline(always)]
63    pub fn variant(&self) -> CC3S_A {
64        match self.bits {
65            0 => CC3S_A::Output,
66            1 => CC3S_A::Ti3,
67            2 => CC3S_A::Ti4,
68            3 => CC3S_A::Trc,
69            _ => unreachable!(),
70        }
71    }
72    ///Checks if the value of the field is `Output`
73    #[inline(always)]
74    pub fn is_output(&self) -> bool {
75        *self == CC3S_A::Output
76    }
77    ///Checks if the value of the field is `Ti3`
78    #[inline(always)]
79    pub fn is_ti3(&self) -> bool {
80        *self == CC3S_A::Ti3
81    }
82    ///Checks if the value of the field is `Ti4`
83    #[inline(always)]
84    pub fn is_ti4(&self) -> bool {
85        *self == CC3S_A::Ti4
86    }
87    ///Checks if the value of the field is `Trc`
88    #[inline(always)]
89    pub fn is_trc(&self) -> bool {
90        *self == CC3S_A::Trc
91    }
92}
93///Field `CC3S` writer - Capture/compare 3 selection
94pub type CC3S_W<'a, const O: u8> =
95    crate::FieldWriterSafe<'a, u32, CCMR2_INPUT_SPEC, u8, CC3S_A, 2, O>;
96impl<'a, const O: u8> CC3S_W<'a, O> {
97    ///CC3 channel is configured as output
98    #[inline(always)]
99    pub fn output(self) -> &'a mut W {
100        self.variant(CC3S_A::Output)
101    }
102    ///CC3 channel is configured as input, IC3 is mapped on TI3
103    #[inline(always)]
104    pub fn ti3(self) -> &'a mut W {
105        self.variant(CC3S_A::Ti3)
106    }
107    ///CC3 channel is configured as input, IC3 is mapped on TI4
108    #[inline(always)]
109    pub fn ti4(self) -> &'a mut W {
110        self.variant(CC3S_A::Ti4)
111    }
112    ///CC3 channel is configured as input, IC3 is mapped on TRC
113    #[inline(always)]
114    pub fn trc(self) -> &'a mut W {
115        self.variant(CC3S_A::Trc)
116    }
117}
118///Field `IC3PSC` reader - Input capture 3 prescaler
119pub type IC3PSC_R = crate::FieldReader<u8, u8>;
120///Field `IC3PSC` writer - Input capture 3 prescaler
121pub type IC3PSC_W<'a, const O: u8> =
122    crate::FieldWriterSafe<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
123///Field `IC3F` reader - Input capture 3 filter
124pub type IC3F_R = crate::FieldReader<u8, u8>;
125///Field `IC3F` writer - Input capture 3 filter
126pub type IC3F_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 4, O>;
127///Field `CC4S` reader - Capture/Compare 4 selection
128pub type CC4S_R = crate::FieldReader<u8, CC4S_A>;
129/**Capture/Compare 4 selection
130
131Value on reset: 0*/
132#[derive(Clone, Copy, Debug, PartialEq, Eq)]
133#[repr(u8)]
134pub enum CC4S_A {
135    ///0: CC4 channel is configured as output
136    Output = 0,
137    ///1: CC4 channel is configured as input, IC4 is mapped on TI4
138    Ti4 = 1,
139    ///2: CC4 channel is configured as input, IC4 is mapped on TI3
140    Ti3 = 2,
141    ///3: CC4 channel is configured as input, IC4 is mapped on TRC
142    Trc = 3,
143}
144impl From<CC4S_A> for u8 {
145    #[inline(always)]
146    fn from(variant: CC4S_A) -> Self {
147        variant as _
148    }
149}
150impl CC4S_R {
151    ///Get enumerated values variant
152    #[inline(always)]
153    pub fn variant(&self) -> CC4S_A {
154        match self.bits {
155            0 => CC4S_A::Output,
156            1 => CC4S_A::Ti4,
157            2 => CC4S_A::Ti3,
158            3 => CC4S_A::Trc,
159            _ => unreachable!(),
160        }
161    }
162    ///Checks if the value of the field is `Output`
163    #[inline(always)]
164    pub fn is_output(&self) -> bool {
165        *self == CC4S_A::Output
166    }
167    ///Checks if the value of the field is `Ti4`
168    #[inline(always)]
169    pub fn is_ti4(&self) -> bool {
170        *self == CC4S_A::Ti4
171    }
172    ///Checks if the value of the field is `Ti3`
173    #[inline(always)]
174    pub fn is_ti3(&self) -> bool {
175        *self == CC4S_A::Ti3
176    }
177    ///Checks if the value of the field is `Trc`
178    #[inline(always)]
179    pub fn is_trc(&self) -> bool {
180        *self == CC4S_A::Trc
181    }
182}
183///Field `CC4S` writer - Capture/Compare 4 selection
184pub type CC4S_W<'a, const O: u8> =
185    crate::FieldWriterSafe<'a, u32, CCMR2_INPUT_SPEC, u8, CC4S_A, 2, O>;
186impl<'a, const O: u8> CC4S_W<'a, O> {
187    ///CC4 channel is configured as output
188    #[inline(always)]
189    pub fn output(self) -> &'a mut W {
190        self.variant(CC4S_A::Output)
191    }
192    ///CC4 channel is configured as input, IC4 is mapped on TI4
193    #[inline(always)]
194    pub fn ti4(self) -> &'a mut W {
195        self.variant(CC4S_A::Ti4)
196    }
197    ///CC4 channel is configured as input, IC4 is mapped on TI3
198    #[inline(always)]
199    pub fn ti3(self) -> &'a mut W {
200        self.variant(CC4S_A::Ti3)
201    }
202    ///CC4 channel is configured as input, IC4 is mapped on TRC
203    #[inline(always)]
204    pub fn trc(self) -> &'a mut W {
205        self.variant(CC4S_A::Trc)
206    }
207}
208///Field `IC4PSC` reader - Input capture 4 prescaler
209pub type IC4PSC_R = crate::FieldReader<u8, u8>;
210///Field `IC4PSC` writer - Input capture 4 prescaler
211pub type IC4PSC_W<'a, const O: u8> =
212    crate::FieldWriterSafe<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 2, O>;
213///Field `IC4F` reader - Input capture 4 filter
214pub type IC4F_R = crate::FieldReader<u8, u8>;
215///Field `IC4F` writer - Input capture 4 filter
216pub type IC4F_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CCMR2_INPUT_SPEC, u8, u8, 4, O>;
217impl R {
218    ///Bits 0:1 - Capture/compare 3 selection
219    #[inline(always)]
220    pub fn cc3s(&self) -> CC3S_R {
221        CC3S_R::new((self.bits & 3) as u8)
222    }
223    ///Bits 2:3 - Input capture 3 prescaler
224    #[inline(always)]
225    pub fn ic3psc(&self) -> IC3PSC_R {
226        IC3PSC_R::new(((self.bits >> 2) & 3) as u8)
227    }
228    ///Bits 4:7 - Input capture 3 filter
229    #[inline(always)]
230    pub fn ic3f(&self) -> IC3F_R {
231        IC3F_R::new(((self.bits >> 4) & 0x0f) as u8)
232    }
233    ///Bits 8:9 - Capture/Compare 4 selection
234    #[inline(always)]
235    pub fn cc4s(&self) -> CC4S_R {
236        CC4S_R::new(((self.bits >> 8) & 3) as u8)
237    }
238    ///Bits 10:11 - Input capture 4 prescaler
239    #[inline(always)]
240    pub fn ic4psc(&self) -> IC4PSC_R {
241        IC4PSC_R::new(((self.bits >> 10) & 3) as u8)
242    }
243    ///Bits 12:15 - Input capture 4 filter
244    #[inline(always)]
245    pub fn ic4f(&self) -> IC4F_R {
246        IC4F_R::new(((self.bits >> 12) & 0x0f) as u8)
247    }
248}
249impl W {
250    ///Bits 0:1 - Capture/compare 3 selection
251    #[inline(always)]
252    #[must_use]
253    pub fn cc3s(&mut self) -> CC3S_W<0> {
254        CC3S_W::new(self)
255    }
256    ///Bits 2:3 - Input capture 3 prescaler
257    #[inline(always)]
258    #[must_use]
259    pub fn ic3psc(&mut self) -> IC3PSC_W<2> {
260        IC3PSC_W::new(self)
261    }
262    ///Bits 4:7 - Input capture 3 filter
263    #[inline(always)]
264    #[must_use]
265    pub fn ic3f(&mut self) -> IC3F_W<4> {
266        IC3F_W::new(self)
267    }
268    ///Bits 8:9 - Capture/Compare 4 selection
269    #[inline(always)]
270    #[must_use]
271    pub fn cc4s(&mut self) -> CC4S_W<8> {
272        CC4S_W::new(self)
273    }
274    ///Bits 10:11 - Input capture 4 prescaler
275    #[inline(always)]
276    #[must_use]
277    pub fn ic4psc(&mut self) -> IC4PSC_W<10> {
278        IC4PSC_W::new(self)
279    }
280    ///Bits 12:15 - Input capture 4 filter
281    #[inline(always)]
282    #[must_use]
283    pub fn ic4f(&mut self) -> IC4F_W<12> {
284        IC4F_W::new(self)
285    }
286    ///Writes raw bits to the register.
287    #[inline(always)]
288    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
289        self.0.bits(bits);
290        self
291    }
292}
293/**capture/compare mode register 2 (input mode)
294
295This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
296
297For information about available fields see [ccmr2_input](index.html) module*/
298pub struct CCMR2_INPUT_SPEC;
299impl crate::RegisterSpec for CCMR2_INPUT_SPEC {
300    type Ux = u32;
301}
302///`read()` method returns [ccmr2_input::R](R) reader structure
303impl crate::Readable for CCMR2_INPUT_SPEC {
304    type Reader = R;
305}
306///`write(|w| ..)` method takes [ccmr2_input::W](W) writer structure
307impl crate::Writable for CCMR2_INPUT_SPEC {
308    type Writer = W;
309    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
310    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
311}
312///`reset()` method sets CCMR2_Input to value 0
313impl crate::Resettable for CCMR2_INPUT_SPEC {
314    const RESET_VALUE: Self::Ux = 0;
315}
py32f0/py32f030/tim1/ccmr2_input.rs

py32f0/py32f030/tim1/
ccmr2_input.rs
