py32f0/py32f030/rtc/
divl.rs

1///Register `DIVL` reader
2pub struct R(crate::R<DIVL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIVL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIVL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIVL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Field `DIVL` reader - RTC prescaler divider register Low
17pub type DIVL_R = crate::FieldReader<u16, u16>;
18impl R {
19    ///Bits 0:15 - RTC prescaler divider register Low
20    #[inline(always)]
21    pub fn divl(&self) -> DIVL_R {
22        DIVL_R::new((self.bits & 0xffff) as u16)
23    }
24}
25/**RTC Prescaler Divider Register Low
26
27This register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
28
29For information about available fields see [divl](index.html) module*/
30pub struct DIVL_SPEC;
31impl crate::RegisterSpec for DIVL_SPEC {
32    type Ux = u32;
33}
34///`read()` method returns [divl::R](R) reader structure
35impl crate::Readable for DIVL_SPEC {
36    type Reader = R;
37}
38///`reset()` method sets DIVL to value 0x8000
39impl crate::Resettable for DIVL_SPEC {
40    const RESET_VALUE: Self::Ux = 0x8000;
41}
py32f0/py32f030/rtc/divl.rs

py32f0/py32f030/rtc/
divl.rs
