py32f0/py32f030/gpiob/
bsrr.rs

1///Register `BSRR` writer
2pub struct W(crate::W<BSRR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<BSRR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<BSRR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<BSRR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22/**Port x set bit y (y= 0..15)
23
24Value on reset: 0*/
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum BS0W_AW {
27    ///1: Sets the corresponding ODx bit
28    Set = 1,
29}
30impl From<BS0W_AW> for bool {
31    #[inline(always)]
32    fn from(variant: BS0W_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36///Field `BS0` writer - Port x set bit y (y= 0..15)
37pub type BS0_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSRR_SPEC, BS0W_AW, O>;
38impl<'a, const O: u8> BS0_W<'a, O> {
39    ///Sets the corresponding ODx bit
40    #[inline(always)]
41    pub fn set(self) -> &'a mut W {
42        self.variant(BS0W_AW::Set)
43    }
44}
45///Field `BS1` writer - Port x set bit y (y= 0..15)
46pub use BS0_W as BS1_W;
47///Field `BS2` writer - Port x set bit y (y= 0..15)
48pub use BS0_W as BS2_W;
49///Field `BS3` writer - Port x set bit y (y= 0..15)
50pub use BS0_W as BS3_W;
51///Field `BS4` writer - Port x set bit y (y= 0..15)
52pub use BS0_W as BS4_W;
53///Field `BS5` writer - Port x set bit y (y= 0..15)
54pub use BS0_W as BS5_W;
55///Field `BS6` writer - Port x set bit y (y= 0..15)
56pub use BS0_W as BS6_W;
57///Field `BS7` writer - Port x set bit y (y= 0..15)
58pub use BS0_W as BS7_W;
59///Field `BS8` writer - Port x set bit y (y= 0..15)
60pub use BS0_W as BS8_W;
61/**Port x set bit y (y= 0..15)
62
63Value on reset: 0*/
64#[derive(Clone, Copy, Debug, PartialEq, Eq)]
65pub enum BR0W_AW {
66    ///1: Resets the corresponding ODx bit
67    Reset = 1,
68}
69impl From<BR0W_AW> for bool {
70    #[inline(always)]
71    fn from(variant: BR0W_AW) -> Self {
72        variant as u8 != 0
73    }
74}
75///Field `BR0` writer - Port x set bit y (y= 0..15)
76pub type BR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, BSRR_SPEC, BR0W_AW, O>;
77impl<'a, const O: u8> BR0_W<'a, O> {
78    ///Resets the corresponding ODx bit
79    #[inline(always)]
80    pub fn reset(self) -> &'a mut W {
81        self.variant(BR0W_AW::Reset)
82    }
83}
84///Field `BR1` writer - Port x reset bit y (y = 0..15)
85pub use BR0_W as BR1_W;
86///Field `BR2` writer - Port x reset bit y (y = 0..15)
87pub use BR0_W as BR2_W;
88///Field `BR3` writer - Port x reset bit y (y = 0..15)
89pub use BR0_W as BR3_W;
90///Field `BR4` writer - Port x reset bit y (y = 0..15)
91pub use BR0_W as BR4_W;
92///Field `BR5` writer - Port x reset bit y (y = 0..15)
93pub use BR0_W as BR5_W;
94///Field `BR6` writer - Port x reset bit y (y = 0..15)
95pub use BR0_W as BR6_W;
96///Field `BR7` writer - Port x reset bit y (y = 0..15)
97pub use BR0_W as BR7_W;
98///Field `BR8` writer - Port x reset bit y (y = 0..15)
99pub use BR0_W as BR8_W;
100impl W {
101    ///Bit 0 - Port x set bit y (y= 0..15)
102    #[inline(always)]
103    #[must_use]
104    pub fn bs0(&mut self) -> BS0_W<0> {
105        BS0_W::new(self)
106    }
107    ///Bit 1 - Port x set bit y (y= 0..15)
108    #[inline(always)]
109    #[must_use]
110    pub fn bs1(&mut self) -> BS1_W<1> {
111        BS1_W::new(self)
112    }
113    ///Bit 2 - Port x set bit y (y= 0..15)
114    #[inline(always)]
115    #[must_use]
116    pub fn bs2(&mut self) -> BS2_W<2> {
117        BS2_W::new(self)
118    }
119    ///Bit 3 - Port x set bit y (y= 0..15)
120    #[inline(always)]
121    #[must_use]
122    pub fn bs3(&mut self) -> BS3_W<3> {
123        BS3_W::new(self)
124    }
125    ///Bit 4 - Port x set bit y (y= 0..15)
126    #[inline(always)]
127    #[must_use]
128    pub fn bs4(&mut self) -> BS4_W<4> {
129        BS4_W::new(self)
130    }
131    ///Bit 5 - Port x set bit y (y= 0..15)
132    #[inline(always)]
133    #[must_use]
134    pub fn bs5(&mut self) -> BS5_W<5> {
135        BS5_W::new(self)
136    }
137    ///Bit 6 - Port x set bit y (y= 0..15)
138    #[inline(always)]
139    #[must_use]
140    pub fn bs6(&mut self) -> BS6_W<6> {
141        BS6_W::new(self)
142    }
143    ///Bit 7 - Port x set bit y (y= 0..15)
144    #[inline(always)]
145    #[must_use]
146    pub fn bs7(&mut self) -> BS7_W<7> {
147        BS7_W::new(self)
148    }
149    ///Bit 8 - Port x set bit y (y= 0..15)
150    #[inline(always)]
151    #[must_use]
152    pub fn bs8(&mut self) -> BS8_W<8> {
153        BS8_W::new(self)
154    }
155    ///Bit 16 - Port x set bit y (y= 0..15)
156    #[inline(always)]
157    #[must_use]
158    pub fn br0(&mut self) -> BR0_W<16> {
159        BR0_W::new(self)
160    }
161    ///Bit 17 - Port x reset bit y (y = 0..15)
162    #[inline(always)]
163    #[must_use]
164    pub fn br1(&mut self) -> BR1_W<17> {
165        BR1_W::new(self)
166    }
167    ///Bit 18 - Port x reset bit y (y = 0..15)
168    #[inline(always)]
169    #[must_use]
170    pub fn br2(&mut self) -> BR2_W<18> {
171        BR2_W::new(self)
172    }
173    ///Bit 19 - Port x reset bit y (y = 0..15)
174    #[inline(always)]
175    #[must_use]
176    pub fn br3(&mut self) -> BR3_W<19> {
177        BR3_W::new(self)
178    }
179    ///Bit 20 - Port x reset bit y (y = 0..15)
180    #[inline(always)]
181    #[must_use]
182    pub fn br4(&mut self) -> BR4_W<20> {
183        BR4_W::new(self)
184    }
185    ///Bit 21 - Port x reset bit y (y = 0..15)
186    #[inline(always)]
187    #[must_use]
188    pub fn br5(&mut self) -> BR5_W<21> {
189        BR5_W::new(self)
190    }
191    ///Bit 22 - Port x reset bit y (y = 0..15)
192    #[inline(always)]
193    #[must_use]
194    pub fn br6(&mut self) -> BR6_W<22> {
195        BR6_W::new(self)
196    }
197    ///Bit 23 - Port x reset bit y (y = 0..15)
198    #[inline(always)]
199    #[must_use]
200    pub fn br7(&mut self) -> BR7_W<23> {
201        BR7_W::new(self)
202    }
203    ///Bit 24 - Port x reset bit y (y = 0..15)
204    #[inline(always)]
205    #[must_use]
206    pub fn br8(&mut self) -> BR8_W<24> {
207        BR8_W::new(self)
208    }
209    ///Writes raw bits to the register.
210    #[inline(always)]
211    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
212        self.0.bits(bits);
213        self
214    }
215}
216/**GPIO port bit set/reset register
217
218This register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
219
220For information about available fields see [bsrr](index.html) module*/
221pub struct BSRR_SPEC;
222impl crate::RegisterSpec for BSRR_SPEC {
223    type Ux = u32;
224}
225///`write(|w| ..)` method takes [bsrr::W](W) writer structure
226impl crate::Writable for BSRR_SPEC {
227    type Writer = W;
228    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
229    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
230}
231///`reset()` method sets BSRR to value 0
232impl crate::Resettable for BSRR_SPEC {
233    const RESET_VALUE: Self::Ux = 0;
234}
py32f0/py32f030/gpiob/bsrr.rs

py32f0/py32f030/gpiob/
bsrr.rs
