py32f0/py32f030/gpioa/
odr.rs

1///Register `ODR` reader
2pub struct R(crate::R<ODR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ODR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ODR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ODR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `ODR` writer
17pub struct W(crate::W<ODR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ODR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ODR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ODR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `OD0` reader - Port output data (y = 0..15)
38pub type OD0_R = crate::BitReader<OD0_A>;
39/**Port output data (y = 0..15)
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum OD0_A {
44    ///0: Set output to logic low
45    Low = 0,
46    ///1: Set output to logic high
47    High = 1,
48}
49impl From<OD0_A> for bool {
50    #[inline(always)]
51    fn from(variant: OD0_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl OD0_R {
56    ///Get enumerated values variant
57    #[inline(always)]
58    pub fn variant(&self) -> OD0_A {
59        match self.bits {
60            false => OD0_A::Low,
61            true => OD0_A::High,
62        }
63    }
64    ///Checks if the value of the field is `Low`
65    #[inline(always)]
66    pub fn is_low(&self) -> bool {
67        *self == OD0_A::Low
68    }
69    ///Checks if the value of the field is `High`
70    #[inline(always)]
71    pub fn is_high(&self) -> bool {
72        *self == OD0_A::High
73    }
74}
75///Field `OD0` writer - Port output data (y = 0..15)
76pub type OD0_W<'a, const O: u8> = crate::BitWriter<'a, u32, ODR_SPEC, OD0_A, O>;
77impl<'a, const O: u8> OD0_W<'a, O> {
78    ///Set output to logic low
79    #[inline(always)]
80    pub fn low(self) -> &'a mut W {
81        self.variant(OD0_A::Low)
82    }
83    ///Set output to logic high
84    #[inline(always)]
85    pub fn high(self) -> &'a mut W {
86        self.variant(OD0_A::High)
87    }
88}
89///Field `OD1` reader - Port output data (y = 0..15)
90pub use OD0_R as OD1_R;
91///Field `OD2` reader - Port output data (y = 0..15)
92pub use OD0_R as OD2_R;
93///Field `OD3` reader - Port output data (y = 0..15)
94pub use OD0_R as OD3_R;
95///Field `OD4` reader - Port output data (y = 0..15)
96pub use OD0_R as OD4_R;
97///Field `OD5` reader - Port output data (y = 0..15)
98pub use OD0_R as OD5_R;
99///Field `OD6` reader - Port output data (y = 0..15)
100pub use OD0_R as OD6_R;
101///Field `OD7` reader - Port output data (y = 0..15)
102pub use OD0_R as OD7_R;
103///Field `OD8` reader - Port output data (y = 0..15)
104pub use OD0_R as OD8_R;
105///Field `OD9` reader - Port output data (y = 0..15)
106pub use OD0_R as OD9_R;
107///Field `OD10` reader - Port output data (y = 0..15)
108pub use OD0_R as OD10_R;
109///Field `OD11` reader - Port output data (y = 0..15)
110pub use OD0_R as OD11_R;
111///Field `OD12` reader - Port output data (y = 0..15)
112pub use OD0_R as OD12_R;
113///Field `OD13` reader - Port output data (y = 0..15)
114pub use OD0_R as OD13_R;
115///Field `OD14` reader - Port output data (y = 0..15)
116pub use OD0_R as OD14_R;
117///Field `OD15` reader - Port output data (y = 0..15)
118pub use OD0_R as OD15_R;
119///Field `OD1` writer - Port output data (y = 0..15)
120pub use OD0_W as OD1_W;
121///Field `OD2` writer - Port output data (y = 0..15)
122pub use OD0_W as OD2_W;
123///Field `OD3` writer - Port output data (y = 0..15)
124pub use OD0_W as OD3_W;
125///Field `OD4` writer - Port output data (y = 0..15)
126pub use OD0_W as OD4_W;
127///Field `OD5` writer - Port output data (y = 0..15)
128pub use OD0_W as OD5_W;
129///Field `OD6` writer - Port output data (y = 0..15)
130pub use OD0_W as OD6_W;
131///Field `OD7` writer - Port output data (y = 0..15)
132pub use OD0_W as OD7_W;
133///Field `OD8` writer - Port output data (y = 0..15)
134pub use OD0_W as OD8_W;
135///Field `OD9` writer - Port output data (y = 0..15)
136pub use OD0_W as OD9_W;
137///Field `OD10` writer - Port output data (y = 0..15)
138pub use OD0_W as OD10_W;
139///Field `OD11` writer - Port output data (y = 0..15)
140pub use OD0_W as OD11_W;
141///Field `OD12` writer - Port output data (y = 0..15)
142pub use OD0_W as OD12_W;
143///Field `OD13` writer - Port output data (y = 0..15)
144pub use OD0_W as OD13_W;
145///Field `OD14` writer - Port output data (y = 0..15)
146pub use OD0_W as OD14_W;
147///Field `OD15` writer - Port output data (y = 0..15)
148pub use OD0_W as OD15_W;
149impl R {
150    ///Bit 0 - Port output data (y = 0..15)
151    #[inline(always)]
152    pub fn od0(&self) -> OD0_R {
153        OD0_R::new((self.bits & 1) != 0)
154    }
155    ///Bit 1 - Port output data (y = 0..15)
156    #[inline(always)]
157    pub fn od1(&self) -> OD1_R {
158        OD1_R::new(((self.bits >> 1) & 1) != 0)
159    }
160    ///Bit 2 - Port output data (y = 0..15)
161    #[inline(always)]
162    pub fn od2(&self) -> OD2_R {
163        OD2_R::new(((self.bits >> 2) & 1) != 0)
164    }
165    ///Bit 3 - Port output data (y = 0..15)
166    #[inline(always)]
167    pub fn od3(&self) -> OD3_R {
168        OD3_R::new(((self.bits >> 3) & 1) != 0)
169    }
170    ///Bit 4 - Port output data (y = 0..15)
171    #[inline(always)]
172    pub fn od4(&self) -> OD4_R {
173        OD4_R::new(((self.bits >> 4) & 1) != 0)
174    }
175    ///Bit 5 - Port output data (y = 0..15)
176    #[inline(always)]
177    pub fn od5(&self) -> OD5_R {
178        OD5_R::new(((self.bits >> 5) & 1) != 0)
179    }
180    ///Bit 6 - Port output data (y = 0..15)
181    #[inline(always)]
182    pub fn od6(&self) -> OD6_R {
183        OD6_R::new(((self.bits >> 6) & 1) != 0)
184    }
185    ///Bit 7 - Port output data (y = 0..15)
186    #[inline(always)]
187    pub fn od7(&self) -> OD7_R {
188        OD7_R::new(((self.bits >> 7) & 1) != 0)
189    }
190    ///Bit 8 - Port output data (y = 0..15)
191    #[inline(always)]
192    pub fn od8(&self) -> OD8_R {
193        OD8_R::new(((self.bits >> 8) & 1) != 0)
194    }
195    ///Bit 9 - Port output data (y = 0..15)
196    #[inline(always)]
197    pub fn od9(&self) -> OD9_R {
198        OD9_R::new(((self.bits >> 9) & 1) != 0)
199    }
200    ///Bit 10 - Port output data (y = 0..15)
201    #[inline(always)]
202    pub fn od10(&self) -> OD10_R {
203        OD10_R::new(((self.bits >> 10) & 1) != 0)
204    }
205    ///Bit 11 - Port output data (y = 0..15)
206    #[inline(always)]
207    pub fn od11(&self) -> OD11_R {
208        OD11_R::new(((self.bits >> 11) & 1) != 0)
209    }
210    ///Bit 12 - Port output data (y = 0..15)
211    #[inline(always)]
212    pub fn od12(&self) -> OD12_R {
213        OD12_R::new(((self.bits >> 12) & 1) != 0)
214    }
215    ///Bit 13 - Port output data (y = 0..15)
216    #[inline(always)]
217    pub fn od13(&self) -> OD13_R {
218        OD13_R::new(((self.bits >> 13) & 1) != 0)
219    }
220    ///Bit 14 - Port output data (y = 0..15)
221    #[inline(always)]
222    pub fn od14(&self) -> OD14_R {
223        OD14_R::new(((self.bits >> 14) & 1) != 0)
224    }
225    ///Bit 15 - Port output data (y = 0..15)
226    #[inline(always)]
227    pub fn od15(&self) -> OD15_R {
228        OD15_R::new(((self.bits >> 15) & 1) != 0)
229    }
230}
231impl W {
232    ///Bit 0 - Port output data (y = 0..15)
233    #[inline(always)]
234    #[must_use]
235    pub fn od0(&mut self) -> OD0_W<0> {
236        OD0_W::new(self)
237    }
238    ///Bit 1 - Port output data (y = 0..15)
239    #[inline(always)]
240    #[must_use]
241    pub fn od1(&mut self) -> OD1_W<1> {
242        OD1_W::new(self)
243    }
244    ///Bit 2 - Port output data (y = 0..15)
245    #[inline(always)]
246    #[must_use]
247    pub fn od2(&mut self) -> OD2_W<2> {
248        OD2_W::new(self)
249    }
250    ///Bit 3 - Port output data (y = 0..15)
251    #[inline(always)]
252    #[must_use]
253    pub fn od3(&mut self) -> OD3_W<3> {
254        OD3_W::new(self)
255    }
256    ///Bit 4 - Port output data (y = 0..15)
257    #[inline(always)]
258    #[must_use]
259    pub fn od4(&mut self) -> OD4_W<4> {
260        OD4_W::new(self)
261    }
262    ///Bit 5 - Port output data (y = 0..15)
263    #[inline(always)]
264    #[must_use]
265    pub fn od5(&mut self) -> OD5_W<5> {
266        OD5_W::new(self)
267    }
268    ///Bit 6 - Port output data (y = 0..15)
269    #[inline(always)]
270    #[must_use]
271    pub fn od6(&mut self) -> OD6_W<6> {
272        OD6_W::new(self)
273    }
274    ///Bit 7 - Port output data (y = 0..15)
275    #[inline(always)]
276    #[must_use]
277    pub fn od7(&mut self) -> OD7_W<7> {
278        OD7_W::new(self)
279    }
280    ///Bit 8 - Port output data (y = 0..15)
281    #[inline(always)]
282    #[must_use]
283    pub fn od8(&mut self) -> OD8_W<8> {
284        OD8_W::new(self)
285    }
286    ///Bit 9 - Port output data (y = 0..15)
287    #[inline(always)]
288    #[must_use]
289    pub fn od9(&mut self) -> OD9_W<9> {
290        OD9_W::new(self)
291    }
292    ///Bit 10 - Port output data (y = 0..15)
293    #[inline(always)]
294    #[must_use]
295    pub fn od10(&mut self) -> OD10_W<10> {
296        OD10_W::new(self)
297    }
298    ///Bit 11 - Port output data (y = 0..15)
299    #[inline(always)]
300    #[must_use]
301    pub fn od11(&mut self) -> OD11_W<11> {
302        OD11_W::new(self)
303    }
304    ///Bit 12 - Port output data (y = 0..15)
305    #[inline(always)]
306    #[must_use]
307    pub fn od12(&mut self) -> OD12_W<12> {
308        OD12_W::new(self)
309    }
310    ///Bit 13 - Port output data (y = 0..15)
311    #[inline(always)]
312    #[must_use]
313    pub fn od13(&mut self) -> OD13_W<13> {
314        OD13_W::new(self)
315    }
316    ///Bit 14 - Port output data (y = 0..15)
317    #[inline(always)]
318    #[must_use]
319    pub fn od14(&mut self) -> OD14_W<14> {
320        OD14_W::new(self)
321    }
322    ///Bit 15 - Port output data (y = 0..15)
323    #[inline(always)]
324    #[must_use]
325    pub fn od15(&mut self) -> OD15_W<15> {
326        OD15_W::new(self)
327    }
328    ///Writes raw bits to the register.
329    #[inline(always)]
330    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
331        self.0.bits(bits);
332        self
333    }
334}
335/**GPIO port output data register
336
337This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
338
339For information about available fields see [odr](index.html) module*/
340pub struct ODR_SPEC;
341impl crate::RegisterSpec for ODR_SPEC {
342    type Ux = u32;
343}
344///`read()` method returns [odr::R](R) reader structure
345impl crate::Readable for ODR_SPEC {
346    type Reader = R;
347}
348///`write(|w| ..)` method takes [odr::W](W) writer structure
349impl crate::Writable for ODR_SPEC {
350    type Writer = W;
351    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
352    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
353}
354///`reset()` method sets ODR to value 0
355impl crate::Resettable for ODR_SPEC {
356    const RESET_VALUE: Self::Ux = 0;
357}
py32f0/py32f030/gpioa/odr.rs

py32f0/py32f030/gpioa/
odr.rs
