py32f0/py32f030/lptim/
cfgr.rs

1///Register `CFGR` reader
2pub struct R(crate::R<CFGR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFGR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFGR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFGR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16///Register `CFGR` writer
17pub struct W(crate::W<CFGR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFGR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFGR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFGR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37///Field `PRESC` reader - Clock prescaler
38pub type PRESC_R = crate::FieldReader<u8, PRESC_A>;
39/**Clock prescaler
40
41Value on reset: 0*/
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43#[repr(u8)]
44pub enum PRESC_A {
45    ///0: /1
46    Div1 = 0,
47    ///1: /2
48    Div2 = 1,
49    ///2: /4
50    Div4 = 2,
51    ///3: /8
52    Div8 = 3,
53    ///4: /16
54    Div16 = 4,
55    ///5: /32
56    Div32 = 5,
57    ///6: /64
58    Div64 = 6,
59    ///7: /128
60    Div128 = 7,
61}
62impl From<PRESC_A> for u8 {
63    #[inline(always)]
64    fn from(variant: PRESC_A) -> Self {
65        variant as _
66    }
67}
68impl PRESC_R {
69    ///Get enumerated values variant
70    #[inline(always)]
71    pub fn variant(&self) -> PRESC_A {
72        match self.bits {
73            0 => PRESC_A::Div1,
74            1 => PRESC_A::Div2,
75            2 => PRESC_A::Div4,
76            3 => PRESC_A::Div8,
77            4 => PRESC_A::Div16,
78            5 => PRESC_A::Div32,
79            6 => PRESC_A::Div64,
80            7 => PRESC_A::Div128,
81            _ => unreachable!(),
82        }
83    }
84    ///Checks if the value of the field is `Div1`
85    #[inline(always)]
86    pub fn is_div1(&self) -> bool {
87        *self == PRESC_A::Div1
88    }
89    ///Checks if the value of the field is `Div2`
90    #[inline(always)]
91    pub fn is_div2(&self) -> bool {
92        *self == PRESC_A::Div2
93    }
94    ///Checks if the value of the field is `Div4`
95    #[inline(always)]
96    pub fn is_div4(&self) -> bool {
97        *self == PRESC_A::Div4
98    }
99    ///Checks if the value of the field is `Div8`
100    #[inline(always)]
101    pub fn is_div8(&self) -> bool {
102        *self == PRESC_A::Div8
103    }
104    ///Checks if the value of the field is `Div16`
105    #[inline(always)]
106    pub fn is_div16(&self) -> bool {
107        *self == PRESC_A::Div16
108    }
109    ///Checks if the value of the field is `Div32`
110    #[inline(always)]
111    pub fn is_div32(&self) -> bool {
112        *self == PRESC_A::Div32
113    }
114    ///Checks if the value of the field is `Div64`
115    #[inline(always)]
116    pub fn is_div64(&self) -> bool {
117        *self == PRESC_A::Div64
118    }
119    ///Checks if the value of the field is `Div128`
120    #[inline(always)]
121    pub fn is_div128(&self) -> bool {
122        *self == PRESC_A::Div128
123    }
124}
125///Field `PRESC` writer - Clock prescaler
126pub type PRESC_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CFGR_SPEC, u8, PRESC_A, 3, O>;
127impl<'a, const O: u8> PRESC_W<'a, O> {
128    #[doc = "/1"]
129    #[inline(always)]
130    pub fn div1(self) -> &'a mut W {
131        self.variant(PRESC_A::Div1)
132    }
133    #[doc = "/2"]
134    #[inline(always)]
135    pub fn div2(self) -> &'a mut W {
136        self.variant(PRESC_A::Div2)
137    }
138    #[doc = "/4"]
139    #[inline(always)]
140    pub fn div4(self) -> &'a mut W {
141        self.variant(PRESC_A::Div4)
142    }
143    #[doc = "/8"]
144    #[inline(always)]
145    pub fn div8(self) -> &'a mut W {
146        self.variant(PRESC_A::Div8)
147    }
148    #[doc = "/16"]
149    #[inline(always)]
150    pub fn div16(self) -> &'a mut W {
151        self.variant(PRESC_A::Div16)
152    }
153    #[doc = "/32"]
154    #[inline(always)]
155    pub fn div32(self) -> &'a mut W {
156        self.variant(PRESC_A::Div32)
157    }
158    #[doc = "/64"]
159    #[inline(always)]
160    pub fn div64(self) -> &'a mut W {
161        self.variant(PRESC_A::Div64)
162    }
163    #[doc = "/128"]
164    #[inline(always)]
165    pub fn div128(self) -> &'a mut W {
166        self.variant(PRESC_A::Div128)
167    }
168}
169///Field `PRELOAD` reader - Registers update mode
170pub type PRELOAD_R = crate::BitReader<PRELOAD_A>;
171/**Registers update mode
172
173Value on reset: 0*/
174#[derive(Clone, Copy, Debug, PartialEq, Eq)]
175pub enum PRELOAD_A {
176    ///0: Registers are updated after each APB bus write access
177    Immediate = 0,
178    ///1: Registers are updated at the end of the current LPTIM period
179    EndOfPeriod = 1,
180}
181impl From<PRELOAD_A> for bool {
182    #[inline(always)]
183    fn from(variant: PRELOAD_A) -> Self {
184        variant as u8 != 0
185    }
186}
187impl PRELOAD_R {
188    ///Get enumerated values variant
189    #[inline(always)]
190    pub fn variant(&self) -> PRELOAD_A {
191        match self.bits {
192            false => PRELOAD_A::Immediate,
193            true => PRELOAD_A::EndOfPeriod,
194        }
195    }
196    ///Checks if the value of the field is `Immediate`
197    #[inline(always)]
198    pub fn is_immediate(&self) -> bool {
199        *self == PRELOAD_A::Immediate
200    }
201    ///Checks if the value of the field is `EndOfPeriod`
202    #[inline(always)]
203    pub fn is_end_of_period(&self) -> bool {
204        *self == PRELOAD_A::EndOfPeriod
205    }
206}
207///Field `PRELOAD` writer - Registers update mode
208pub type PRELOAD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CFGR_SPEC, PRELOAD_A, O>;
209impl<'a, const O: u8> PRELOAD_W<'a, O> {
210    ///Registers are updated after each APB bus write access
211    #[inline(always)]
212    pub fn immediate(self) -> &'a mut W {
213        self.variant(PRELOAD_A::Immediate)
214    }
215    ///Registers are updated at the end of the current LPTIM period
216    #[inline(always)]
217    pub fn end_of_period(self) -> &'a mut W {
218        self.variant(PRELOAD_A::EndOfPeriod)
219    }
220}
221impl R {
222    ///Bits 9:11 - Clock prescaler
223    #[inline(always)]
224    pub fn presc(&self) -> PRESC_R {
225        PRESC_R::new(((self.bits >> 9) & 7) as u8)
226    }
227    ///Bit 22 - Registers update mode
228    #[inline(always)]
229    pub fn preload(&self) -> PRELOAD_R {
230        PRELOAD_R::new(((self.bits >> 22) & 1) != 0)
231    }
232}
233impl W {
234    ///Bits 9:11 - Clock prescaler
235    #[inline(always)]
236    #[must_use]
237    pub fn presc(&mut self) -> PRESC_W<9> {
238        PRESC_W::new(self)
239    }
240    ///Bit 22 - Registers update mode
241    #[inline(always)]
242    #[must_use]
243    pub fn preload(&mut self) -> PRELOAD_W<22> {
244        PRELOAD_W::new(self)
245    }
246    ///Writes raw bits to the register.
247    #[inline(always)]
248    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
249        self.0.bits(bits);
250        self
251    }
252}
253/**Configuration Register
254
255This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
256
257For information about available fields see [cfgr](index.html) module*/
258pub struct CFGR_SPEC;
259impl crate::RegisterSpec for CFGR_SPEC {
260    type Ux = u32;
261}
262///`read()` method returns [cfgr::R](R) reader structure
263impl crate::Readable for CFGR_SPEC {
264    type Reader = R;
265}
266///`write(|w| ..)` method takes [cfgr::W](W) writer structure
267impl crate::Writable for CFGR_SPEC {
268    type Writer = W;
269    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
270    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
271}
272///`reset()` method sets CFGR to value 0
273impl crate::Resettable for CFGR_SPEC {
274    const RESET_VALUE: Self::Ux = 0;
275}
py32f0/py32f030/lptim/cfgr.rs

py32f0/py32f030/lptim/
cfgr.rs
